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"yih cm"的相關文件
顯示項目 1-13 / 13 (共1頁)
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| 國立交通大學 |
2019-04-02T05:59:32Z |
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
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Yih, CM; Cheng, SM; Chung, SS |
| 國立交通大學 |
2019-04-02T05:58:52Z |
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
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Cheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS |
| 國立交通大學 |
2014-12-08T15:49:16Z |
New insight into the degradation mechanism of nitride spacer with different post-oxide in submicron LDD n-MOSFET's
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Yih, CM; Wang, CL; Chung, SS; Wu, CC; Tan, W; Wu, HJ; Pi, S; Huang, D |
| 國立交通大學 |
2014-12-08T15:47:24Z |
A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
|
Yih, CM; Cheng, SM; Chung, SS |
| 國立交通大學 |
2014-12-08T15:46:14Z |
A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:44:20Z |
New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistors
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Chung, SS; Chen, SJ; Yang, WJ; Yih, CM; Yang, JJ |
| 國立交通大學 |
2014-12-08T15:44:13Z |
Characterization of hot-hole injection induced SILC and related disturbs in flash memories
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Yih, CM; Ho, ZH; Liang, MS; Chung, SS |
| 國立交通大學 |
2014-12-08T15:27:35Z |
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
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Yih, CM; Chung, SS; Hsu, CCH |
| 國立交通大學 |
2014-12-08T15:27:25Z |
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:27:23Z |
Performance and reliability evaluations of P-channel flash memories with different programming schemes
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Chung, SS; Kuo, SN; Yih, CM; Chao, TS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
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Chung, SS; Chen, SJ; Yih, CM; Yang, WJ; Chao, TS |
| 國立交通大學 |
2014-12-08T15:26:55Z |
N-channel versus P-channel flash EEPROM - Which one has better reliabilities
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Chung, SS; Liaw, ST; Yih, CM; Ho, ZH; Lin, CJ; Kuo, DS; Liang, MS |
| 國立交通大學 |
2014-12-08T15:01:20Z |
A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
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Cheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS |
顯示項目 1-13 / 13 (共1頁)
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