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"yotsuyanagi h"的相关文件
显示项目 21-30 / 30 (共1页)
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| 國立臺灣科技大學 |
2016 |
A power supply circuit for interconnect tests based on injected charge volume of 3D IC
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Ohtani, K;Hashizume, M;Suga, D;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
A built-in defective level monitor of resistive open defects in 3D ICs with logic gates
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Hashizume, M;Odoriba, A;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops
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Ali, F.A.B;Hashizume, M;Ikiri, Y;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs by injected charge volume
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Suga, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit
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Nanbara, K.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
A testable design for electrical interconnect tests of 3D ICs
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Odoriba, A.;Umezu, S.;Hashizume, M.;Yotsuyanagi, H.;Ali, F.A.B.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs without boundary scan flip flops
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Hashizume, M;Umezu, S;Ikiri, Y;Ali, F.A.B;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC
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Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z. |
| 國立臺灣科技大學 |
2013 |
Built-in IDDT appearance time sensor for detecting open faults in 3D IC
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Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
DFT for supply current testing to detect open defects at interconnects in 3D ICs
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Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.;Roth, Z. |
显示项目 21-30 / 30 (共1页)
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