| 臺大學術典藏 |
2021-09-04T06:19:20Z |
Hepatitis B virus genotypes and hepatocellular carcinoma in Japan [4]
|
Fujie H.; Moriya K.; Shintani Y.; Yotsuyanagi H.; Iino S.; Kimura S.; Koike K.; JIA-HORNG KAO; Chen D.-S. |
| 國立臺灣科技大學 |
2020 |
Temperature Sensing with a Relaxation Oscillator in CMOS ICs
|
Sako, F.;Ikiri, Y.;Hashizume, M.;Yotsuyanagi, H.;Yokoyama, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2020 |
Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards
|
Kanda, M.;Hashizume, M.;Ali, F.A.B.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2020 |
Fault-Aware Dependability Enhancement Techniques for Flash Memories
|
Lu, S.-K.;Yu, S.-C.;Hsu, C.-L.;Sun, C.-T.;Hashizume, M.;Yotsuyanagi, H. |
| 國立臺灣科技大學 |
2020 |
Temperature Sensing with a Relaxation Oscillator in CMOS ICs
|
Sako, F.;Ikiri, Y.;Hashizume, M.;Yotsuyanagi, H.;Yokoyama, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2019 |
Resistive open defect detection in SoCs by a test method based on injected charge volume after test input application
|
Matsumoto, Y.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2019 |
Stand-by mode test method of interconnects between dies in 3d ICs with IEEE 1149.1 test circuits
|
Kanda, M.;Yabui, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 臺大學術典藏 |
2018-09-10T03:49:12Z |
Hepatitis B virus genotypes and hepatocellular carcinoma in Japan [4]
|
Fujie, H.;Moriya, K.;Shintani, Y.;Yotsuyanagi, H.;Iino, S.;Kimura, S.;Koike, K.;Kao, J.-H.;Chen, D.-S.; JIA-HORNG KAO |
| 國立臺灣科技大學 |
2018 |
A design for testability of open defects at interconnects in 3D stacked ICs
|
Ashikin F.; Hashizume M.; Yotsuyanagi H.; Lu S.-K.; Roth Z. |
| 國立臺灣科技大學 |
2018 |
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type
|
Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2018 |
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume
|
Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2018 |
Open defect detection with a built-in test circuit by IDDT appearance time in CMOS ICs
|
Kambara A.; Yotsuyanagi H.; Miyoshi D.; Hashizume M.; Lu S.-K. |
| 國立臺灣科技大學 |
2018 |
Fault-aware page address remapping techniques for enhancing yield and reliability of flash memories
|
Lu S.-K.; Yu S.-C.; Hashizume M.; Yotsuyanagi H. |
| 國立臺灣科技大學 |
2017 |
Electrical tests for capacitive open defects in assembled PCBs
|
Alia, F.A.B.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
Electrical test of resistive and capacitive open defects at data bus in 3D memory IC
|
Hashizume, M.;Shiraishi, Y.;Yotsuyanagi, H.;Yokoyama, H.;Tada, Tada T.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs
|
Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
A built-in current sensor made of a comparator of offset cancellation type for electrical interconnect tests of 3D ICs
|
Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
A built-in electrical test circuit for detecting open leads in assembled PCB circuits
|
Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z. |
| 國立臺灣科技大學 |
2016 |
Electrical interconnect test of solder joint part with boundary scan flip flops and a built-in test circuit
|
Hashizume, M;Ikiri, Y;Konishi, T;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
A built-in test circuit for electrical interconnect testing of open defects in assembled PCBs
|
Widiant, Hashizume M;Suenaga, Suenaga S;Yotsuyanagi, H;Ono, A;Lu, S.-K;Roth, Z. |
| 國立臺灣科技大學 |
2016 |
A power supply circuit for interconnect tests based on injected charge volume of 3D IC
|
Ohtani, K;Hashizume, M;Suga, D;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
A built-in defective level monitor of resistive open defects in 3D ICs with logic gates
|
Hashizume, M;Odoriba, A;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops
|
Ali, F.A.B;Hashizume, M;Ikiri, Y;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs by injected charge volume
|
Suga, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit
|
Nanbara, K.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
A testable design for electrical interconnect tests of 3D ICs
|
Odoriba, A.;Umezu, S.;Hashizume, M.;Yotsuyanagi, H.;Ali, F.A.B.;Lu, S.-K. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs without boundary scan flip flops
|
Hashizume, M;Umezu, S;Ikiri, Y;Ali, F.A.B;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC
|
Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z. |
| 國立臺灣科技大學 |
2013 |
Built-in IDDT appearance time sensor for detecting open faults in 3D IC
|
Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K. |
| 國立臺灣科技大學 |
2013 |
DFT for supply current testing to detect open defects at interconnects in 3D ICs
|
Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.;Roth, Z. |
