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"yu c"的相關文件
顯示項目 111-120 / 231 (共24頁)
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| 臺大學術典藏 |
2018-09-10T08:14:41Z |
Perfect shuffling for cycle efficient puncturer and interleaver for software defined radio
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Lin, J.-C.;Hsieh, M.;Fan-Chiang, M.-J.;Mao, S.-Y.;Yu, C.;Chen, S.-J.;Hu, Y.H.; Lin, J.-C.; Hsieh, M.; Fan-Chiang, M.-J.; Mao, S.-Y.; Yu, C.; Chen, S.-J.; Hu, Y.H.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T08:09:49Z |
Demonstration of edge roughness effect on the magnetization reversal of spin valve submicron wires
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Chiang, T.W.; Chang, L.J.; Yu, C.; Huang, S.Y.; Chen, D.C.; Yao, Y.D.; Lee, S.F.; Chiang, T.W.; Chang, L.J.; Yu, C.; Huang, S.Y.; Chen, D.C.; Yao, Y.D.; Lee, S.F.; SSU-YEN HUANG |
| 臺大學術典藏 |
2018-09-10T07:39:15Z |
The development and evaluation of the citizen telehealth care service system: Case study in Taipei
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Yu, C.;Yang, J.-J.;Chen, J.-G.;Liu, C.-S.;Chen, C.-G.;Lin, M.-L.;Liu, P.-L.;Yao, G.;Lin, C.-W.; Yu, C.; Yang, J.-J.; Chen, J.-G.; Liu, C.-S.; Chen, C.-G.; Lin, M.-L.; Liu, P.-L.; Yao, G.; Lin, C.-W.; CHII-WANN LIN; KAI-PING GRACE YAO |
| 臺大學術典藏 |
2018-09-10T07:36:35Z |
Design of an efficient VLSI architecture for 2-D discrete wavelet transforms
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Yu, C.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:33Z |
Parallel implementation of convolution encoder for software defined radio on DSP architecture
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SAO-JIE CHEN; Hu, Y.H.; Lin, J.-C.;Yu, C.;Yen, M.-H.;Hsiung, P.-A.;Chen, S.-J.;Hu, Y.H.; Lin, J.-C.; Yu, C.; Yen, M.-H.; Hsiung, P.-A.; Chen, S.-J. |
| 臺大學術典藏 |
2018-09-10T07:36:33Z |
Design of a high-speed bloc k interleaving/deinterleaving architecture for wireless communication applications
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Yu, C.;Yen, M.-H.;Hsiung, P.-A.;Chen, S.-J.; Yu, C.; Yen, M.-H.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T07:27:39Z |
Activation of topoisomerase II-mediated excision of chromosomal DNA loops during oxidative stress
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Li, T.-K.;Chen, A.Y.;Yu, C.;Mao, Y.;Wang, H.;Liu, L.F.; TSAI-KUN LI |
| 臺大學術典藏 |
2018-09-10T06:31:53Z |
Ensemble dependent matrix methodology for probabilistic-based fault-tolerant nanoscale circuit design
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Rao, H.; Chen, J.; Yu, C.; Ang, W.T.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement
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Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T06:31:52Z |
A clock-fault tolerant architecture and circuit for reliable nanoelectronics system
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Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU |
顯示項目 111-120 / 231 (共24頁)
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