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"yu hui jung"的相關文件
顯示項目 21-30 / 36 (共4頁)
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| 國立臺灣大學 |
1986-09 |
Integrated Entry and Verification System for VLSI Design
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-09 |
Integrated VLSI Design System - Main System Design
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Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D. |
| 國立臺灣大學 |
1986-09 |
Multiple-Level Abstraction for Hierarchical VLSI Storage System
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Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D. |
| 國立臺灣大學 |
1986-09 |
Netlist-Driven Cell-Layout Editor System
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-09 |
Private Database Management System for VLSI Design
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Parng, T. P.; 馮武雄; 于惠中; Chen, C. F.; Cheng, K. D.; Parng, T. P.; Feng, Wu-Shiung; Yu, Hui-Jung; Chen, C. F.; Cheng, K. D. |
| 國立臺灣大學 |
1986-09 |
Three Layer Routing Algorithms for VLSI Design
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馮武雄; Parng, T. P.; 于惠中; Chen, C. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, C. F. |
| 國立臺灣大學 |
1986-08 |
Hierarchical Timing Verification System for Multiple Clocked Logic Circuit
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Tyan, C. Y.; 馮武雄; 于惠中; Yeh, T. S.; Tyan, C. Y.; Feng, Wu-Shiung; Yu, Hui-Jung; Yeh, T. S. |
| 國立臺灣大學 |
1986 |
An Interactive Symbolic Layout System for Integrated-Circuit Design - HISLID
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馮武雄; 于惠中; Feng, Wu-Shiung; Yu, Hui-Jung |
| 國立臺灣大學 |
1986 |
Parallel Algorithm and Architecture for Solving Covariance Eigen System
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Jou, I. C.; Hu, Y. H.; 于惠中; 馮武雄; Jou, I. C.; Hu, Y. H.; Yu, Hui-Jung; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985-09 |
Automatic VLSI Circuit Synthesizer System Vol.1:A Programming Logic Array (PLA) Reduction and Generation System
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馮武雄; Parng, T. P.; 于惠中; Chen, S. J.; Sun, L. F.; Feng, Wu-Shiung; Parng, T. P.; Yu, Hui-Jung; Chen, S. J.; Sun, L. F. |
顯示項目 21-30 / 36 (共4頁)
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