臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立高雄師範大學	2009-12	A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator	Jsung-Mo Shen;Wei-Bin Yang;Chang-Yu Hsieh;Yu-Lung Lo; 羅有龍
朝陽科技大學	2009-10	Fault Tolerant Searching in Real-valued Feature Index for Music Databases	羅有隆; Yu-lung Lo; Chien-Chi Huang; Ling-Yi Tsai
國立高雄師範大學	2009-09	Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique	Ting-Sheng Chao;Yu-Lung Lo;Wei-Bin Yang;Kuo-Hsing Cheng; 羅有龍
朝陽科技大學	2009-08-01	Efficient Memory Saving Scheme of Multi-Feature Indexing for Music Databases	羅有隆; Yu-Lung Lo;Chun-Hsiung Wang
朝陽科技大學	2009-08	Efficient Memory Saving Scheme of Multi-Feature Indexing for Music Databases	羅有隆; Yu-Lung Lo;Chun-Hsiung Wang
國立高雄師範大學	2009-08	A 0.5 V Phase-Locked Loop in 90nm CMOS Process	Kuo-Hsing Cheng;Jing-Shiuan Huang;Yu-Chang Tsai;Chao-Chang Chiu;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2009-08	A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator	Jsung-Mo Shen;Wei-Bin Yang;Chang-Yu Hsieh;Yu-Lung Lo; 羅有龍
朝陽科技大學	2009-07	Scalable Multi-feature Index Structure for Music Databases	羅有隆; Yu-Lung Lo; Chu-Hui Lee; Chun-Hsiung Wang
國立高雄師範大學	2009-06	High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2009-05	Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2009-02	Vernier Caliper and Equivalent-Signal Sampling for Built-in Jitter Measurement System	Shu-Yu Jiang;Chan-Wei Huang;Yu-Lung Lo;Kuo-Hsing Cheng; 羅有龍
朝陽科技大學	2009-01	Real-valued Feature Indexing for Music Databases	羅有隆; Yu-lung Lo;Ling-yi Tsai
國立高雄師範大學	2008-08	Ultra-Low-Voltage Phase-Locked Loop with Bulk-Input VCO	Yu-Lung Lo;Wei-Bin Yang;Ting-Sheng Chao;Jiunn-Way Miaw;Jing-Shiuan Huang;Kuo-Hsing Cheng; 羅有龍
國立高雄師範大學	2008-04	Spread-Spectrum Clock Generator Using Fractional–N PLL Controlled Delta-Sigma Modulator for Serial-ATA III	Kuo-Hsing Cheng;Cheng-Laing Hung;Chih-Hsien Chang;Yu-Lung Lo;Wei-Bin Yang;Jiunn-Way Miaw; 羅有龍
朝陽科技大學	2008	A Unified Framework for Cluster Manager Election and Clustering Mechanism in Mobile Ad Hoc Networks	王淑卿;潘信宏;嚴國慶;羅有隆; Shu-Ching Wang; Hsin-Hung Pan; Kuo-Qin Yan; Yu-Lung Lo
國立高雄師範大學	2007-12	A Phase Interpolator for Sub-1V and High Frequency for Clock and Data Recovery	Kuo-Hsing Cheng;Pei-Kai Tseng;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2007-11	Analysis and Design of Ultra Low VDD Circuit	Ting-Sheng Chao;Chung-Yu Chang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2007-07	A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency Range Selector for Multiphase Clock Generator	Kuo-Hsing Chen;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2006-12	A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler	Ting-Sheng Jau;Wei-Bin Yang;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2006-05	A 100MHz-1GHz Adaptive Bandwidth Phase-Locked Loop in 90nm Process	Kuo-Hsing Cheng;Kai-Fei Chang;Yu-Lung Lo;Ching-Wen Lai;Yuh-Kuang Tseng; 羅有龍
國立高雄師範大學	2005-09	A Fast-Lock Mixed-Mode DLL with Wide-Range Operation and Multiphase Outputs	Kuo-Hsing Cheng;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2005-05	A Phase-detect Synchronous Mirror Delay for Fast Clock Skew-compensation Circuits	Kuo-Hsing Cheng;Chen-Lung Wu;Yu-Lung Lo;Chia-Wei Su; 羅有龍
國立高雄師範大學	2004-09	A Fast-Lock DLL with Power-On Reset Circuit	Kuo-Hsing Cheng;Yu-Lung Lo;Shu-Yu Jiang; 羅有龍
國立高雄師範大學	2004-08	A CMOS VCO for 1V, 1GHz PLL Applications	Kuo-Hsing Cheng;Ching-Wen Lai;Yu-Lung Lo; 羅有龍
國立高雄師範大學	2004-08	A Phase-Locked Pulse Width Control Loop with Programmable Duty Cycle	Kuo-Hsing Cheng;Chia-Wei Su;Cheng-Lung Wu;Yu-Lung Lo; 羅有龍

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