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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:48:24Z |
Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond
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Yu, Ming H.; Li, J. H.; Lin, H. H.; Chen, C. H.; Ku, K. C.; Nieh, C. F.; Hisa, H.; Sheu, Y. M.; Tsai, C. W.; Wang, Y. L.; Chu, H. Y.; Cheng, H. C.; Lee, T. L.; Chen, S. C.; Liang, M. S. |
| 國立交通大學 |
2014-12-08T15:39:18Z |
A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications
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Liao, Ta-Chuan; Wu, Chun-Yu; Chen, Sheng-Kai; Yu, Ming H.; Kang, Tsung-Kuei; Cheng, Huang-Chung |
| 國立交通大學 |
2014-12-08T15:28:53Z |
Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN-Alumina-Nitride-Vacuum-Silicon Structure
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Wu, Chun-Yu; Liu, Yen-Ting; Liao, Ta-Chuan; Yu, Ming H.; Cheng, Huang-Chung |
| 國立交通大學 |
2014-12-08T15:24:26Z |
A Novel Polysilicon Field-Enhanced Nanowire Thin-Film Transistor with the TiN-Hafnia-Nitride-Vacuum-Silicon (THNVAS) Structure for Nonvolatile Memory Applications
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Wu, Chun-Yu; Liao, Ta-Chuan; Liu, Yen-Ting; Yu, Ming H.; Cheng, Huang-Chung |
| 國立交通大學 |
2014-12-08T15:21:19Z |
A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure
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Liao, Ta-Chuan; Chen, Sheng-Kai; Yu, Ming H.; Wu, Chun-Yu; Kang, Tsung-Kuei; Chien, Feng-Tso; Liu, Yen-Ting; Lin, Chia-Min; Cheng, Huang-Chung |
| 國立交通大學 |
2014-12-08T15:14:27Z |
Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation
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Wu, Chun-Yu; Liao, Ta-Chuan; Yu, Ming-H; Chen, Sheng-Kai; Tsai, Chung-Min; Cheng, Huang-Chung |
| 國立交通大學 |
2014-12-08T15:11:07Z |
Novel gate-all-around poly-Si TFTs with multiple nanowire channels
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Liao, Ta-Chuan; Tu, Shih-Wei; Yu, Ming H.; Lin, Wei-Kai; Liu, Cheng-Chin; Chang, Kuo-Jui; Tai, Ya-Hsiang; Cheng, Huang-Chung |
Showing items 1-7 of 7 (1 Page(s) Totally)
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