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| 國立交通大學 |
2017-04-21T06:49:48Z |
Design and Optimization Methodology for 3D RRAM Arrays
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Deng, Yexin; Chen, Hong-Yu; Gao, Bin; Yu, Shimeng; Wu, Shih-Chieh; Zhao, Liang; Chen, Bing; Jiang, Zizhen; Liu, Xiaoyan; Hou, Tuo-Hung; Nishi, Yoshio; Kang, Jinfeng; Wong, H. -S. Philip |
| 國立交通大學 |
2016-03-28T00:05:45Z |
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning
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Chen, Pai-Yu; Lin, Binbin; Wang, I-Ting; Hou, Tuo-Hung; Ye, Jieping; Vrudhula, Sarma; Seo, Jae-sun; Cao, Yu; Yu, Shimeng |
| 國立交通大學 |
2015-12-02T03:00:54Z |
Improved Multi-level Control of RRAM Using Pulse-Train Programming
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Zhao, Liang; Chen, Hong-Yu; Wu, Shih-Chieh; Jiang, Zizhen; Yu, Shimeng; Hou, Tuo-Hung; Wong, H. -S Philip; Nishi, Yoshio |
| 國立交通大學 |
2015-12-02T02:59:34Z |
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
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Gao, Ligang; Wang, I-Ting; Chen, Pai-Yu; Vrudhula, Sarma; Seo, Jae-Sun; Cao, Yu; Hou, Tuo-Hung; Yu, Shimeng |
Showing items 1-4 of 4 (1 Page(s) Totally)
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