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Showing items 1-6 of 6 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:50:06Z |
A Subthreshold SRAM with Embedded Data-Aware Write-Assist and Adaptive Data-Aware Keeper
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Chiu, Yi-Wei; Hu, Yu-Hao; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2017-04-21T06:49:05Z |
A 28nm 36kb High Speed 6T SRAM with Source Follower PMOS Read and Bit-Line Under-Drive
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Hong, Chi-Hao; Chiu, Yi-Wei; Zhao, Jun-Kai; Jou, Shyh-Jye; Wang, Wen-Tai; Lee, Reed |
| 國立交通大學 |
2017-04-21T06:48:56Z |
Subthreshold SRAM Macro Design with Pulse-Controlled Dynamic Voltage Scaling (PC-DVS)
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Zhao, Jun-Kai; Chiu, Yi-Wei; Jou, Shyh-Jye; Chu, Yuan-Hua |
| 國立交通大學 |
2014-12-12T02:44:30Z |
次微米內嵌式記憶體之低功耗設計
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趙俊凱; Zhao, Jun-Kai; 周世傑; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:36:49Z |
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
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Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Chu, Yuan-Hua; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:36:13Z |
A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
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Chiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te |
Showing items 1-6 of 6 (1 Page(s) Totally)
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