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| 臺大學術典藏 |
2021-04-21T23:30:01Z |
3D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafers
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Su, C. J.; Huang, M. K.; Lee, K. S.; Hu, V. P.H.; Ying-Fang Huang; Zheng, B. C.; Yao, C. H.; Lin, N. C.; Kao, K. H.; Hong, T. C.; Sung, P. J.; Wu, C. T.; Yu, T. Y.; Lin, K. L.; Tseng, Y. C.; Lin, C. L.; Lee, Y. J.; Chao, T. S.; Li, J. Y.; Wu, W. F.; Shieh, J. M.; Wang, Y. H.; Yeh, W. K. |
| 國立成功大學 |
2020 |
3D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafers
|
Su, C.J.;Huang, M.K.;Lee, K.S.;Hu, V.P.H.;Huang, Y.F.;Zheng, B.C.;Yao, C.H.;Lin, N.C.;Kao, Kao K.H.;Hong, T.C.;Sung, P.J.;Wu, C.T.;Yu, T.Y.;Lin, K.L.;Tseng, Y.C.;Lin, C.L.;Lee, Y.J.;Chao, T.S.;Li, J.Y.;Wu, Wu W.F.;Shieh, J.M.;Wang, Y.H.;Yeh, W.K. |
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