| 臺大學術典藏 |
2018-09-10T06:03:13Z |
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines
|
J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T06:03:14Z |
A routability constrained scan chain ordering technique for test power reduction
|
X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T06:03:14Z |
A period tracking based on-chip sinusoidal jitter extraction technique
|
C.-Y. Kuo; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T06:03:14Z |
An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing
|
S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T06:03:14Z |
A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter
|
J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T06:03:15Z |
A low-power oscillator mixer in 0.18-um CMOS technology
|
LIANG-HUNG LU; H. Wang; T.-P. Wang; C.-C. Chang; R.-C. Liu; M.-D. Tsai; K.-J. Sun; Y.-T. Chang; L.-H. Lu |
| 臺大學術典藏 |
2018-09-10T06:03:15Z |
A wide-tuning-range CMOS VCO with a differential tunable active inductor
|
L.-H. Lu; H.-H. Hsieh; Y.-T. Liao; LIANG-HUNG LU |
| 臺大學術典藏 |
2018-09-10T06:03:15Z |
A harmonic injection-locked frequency divider in 0.18-mu m SiGeBiCMOS
|
J. Yeh; C.-Y. Lee; J. Chern; LIANG-HUNG LU; H. Wang; L.-H. Lu; C.-S. Lin; J.-C. Chien |
| 臺大學術典藏 |
2018-09-10T06:03:15Z |
A low-phase-noise K-band CMOS VCO
|
H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU |
| 臺大學術典藏 |
2018-09-10T06:03:16Z |
Integrated CMOS power sensors for RF BIST applications
|
H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU |
| 臺大學術典藏 |
2018-09-10T06:03:17Z |
A Mixed-Signal GFSK Demodulator for Bluetooth
|
T.-C. Lee; C.-C. Chen; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T06:03:17Z |
The design and analysis of a Miller Divider Based Clock Generator for MBOA-UWB Application
|
T.-C. Lee; Y.-C. Huang; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T06:03:17Z |
The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application
|
T.-C. Lee; K.-J. Hsiao; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T06:03:18Z |
A Spur-Suppression Technique for Phase-Locked Frequency Synthesizers
|
W.-L. Lee; TAI-CHENG LEE; T.-C. Lee |
| 臺大學術典藏 |
2018-09-10T06:03:18Z |
CRC BIST: A Low Peak Power Self Technique
|
Bo-Hua Chen; J. C.-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T06:03:19Z |
Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique
|
Y. L Kao; W. S. Chuang; J. C. M Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T06:03:19Z |
VLSI Test Principles and Architectures
|
CHIEN-MO LI; et. al.; Wen; Wu; Wang |
| 臺大學術典藏 |
2018-09-10T06:03:19Z |
A 0.8-V 0.25-mW Current-Mirror OTA with 160-MHz GBW in 0.18-μm CMOS
|
C.-K. Wu; M.-C. Tsai; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T06:03:20Z |
A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.3-μm CMOS
|
T.-H. Lin; C.-C. Chi; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T06:03:20Z |
A Low-Power Asymmetrical MICS Wireless Interface and Transceiver Design for Medical Imaging
|
Y.-H. Liu; C.-J. Tung; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T06:03:20Z |
Low-Power Radio Design for Wireless Smart Sensor Networks
|
W.-C. Fang; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T06:03:20Z |
Linearized Fractional-N Synthesizer Having a Gated Offset
|
Tsung-Hsien Lin; Hung-Ming Chien; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T06:03:21Z |
High Speed Differential Signaling Logic Gate and Applications Thereof
|
Tsung-Hsien Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T06:03:21Z |
Linearized Fractional-N Synthesizer with Fixed Charge Pump Offset
|
Hung-Ming Chien; Tsung-Hsien Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T06:03:21Z |
An Analog Open-Loop VCO Calibration Method
|
Tsung-Hsien Lin; TSUNG-HSIEN LIN |
