| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
BIST Design Optimization for Large-Scale Embedded Memory Cores
|
T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Electronic Design Automation
|
J. C.-M. Li;M. Hsiao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
包含未知訊號之測試結果壓縮設計
|
王偉哲;李建模; 王偉哲 李建模; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
|
Chung-Ping Chen; Chris C. N. Chu; D. F. Wong; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Noise-Aware Repeater Insertion and Wire-Sizing for On-chip Interconnect Using Hierarchical Moment-Matching
|
Chung-Ping Chen; N. Menezes; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Error-bounded Pade Approximation via Bilinear Conformal Transformation
|
Chung-Ping Chen; D.F. Wong; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
Spec-based Repeater Insertion and Wire-Sizing for On-chip Interconnect
|
N. Menezes; Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs
|
T.-H. Lin;C.-L. Ti;Y.-H. Liu; T.-H. Lin; C.-L. Ti; Y.-H. Liu; Lin, Tsung-Hsien |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
A 200-pJ/b MUX-based RF Transmitter for Implantable Multi-Channel Neural Recording
|
Y.-H. Liu;C.-L. Li;T.-H. Lin; Y.-H. Liu; C.-L. Li; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
Wireless Integrated Network Sensors (WINS)
|
TSUNG-HSIEN LIN; G. Asada; I. Bhatti; T.-H. Lin; S. Natkunanthanan; F. Newberg; R. Rofougaran; A. Sipos; S. Valoff; G. J. Pottie; W. J. Kaiser |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
A Low-Power VLSI Neural Processor Design for Image Data Compression in a SOI CMOS Technology
|
W. Fang; E. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A Super-Regenerative ASK Receiver with Delta-Sigma Pulse-width Digitizer and SAR-based Fast Frequency Calibration for MICS Applications
|
Y.-H. Liu;H.-H. Liu;T.-H. Lin; Y.-H. Liu; H.-H. Liu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-μm CMOS
|
W.-H. Chiu;Y.-H. Huang;T.-H. Lin; W.-H. Chiu; Y.-H. Huang; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A Time-Domain-Based Self-Calibrated Analog-to-Digital Converter With A Linear Voltage-to-Delay Circuit in 0.18-μm CMOS
|
C.-H. Yang;W.-H. Chiu;T.-H. Lin; C.-H. Yang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-μm CMOS
|
W.-H. Chiu;T.-S. Chang;T.-H. Lin; W.-H. Chiu; T.-S. Chang; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
Delta sigma modulator and method for compensating delta sigma modulators for loop delay
|
Chan-Hsiang Weng;Tsung-Hsien Lin; Chan-Hsiang Weng; Tsung-Hsien Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
Scalable Don't Care Based Logic Optimization and Resynthesis
|
Alan Mishchenko;Robert K. Brayton;Jie-Hong R. Jiang;Stephen Jang; Alan Mishchenko; Robert K. Brayton; Jie-Hong R. Jiang; Stephen Jang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-μm CMOS
|
K.-C. Liao;P.-S. Huang;W.-H. Chiu;T.-H. Lin; K.-C. Liao; P.-S. Huang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:11Z |
Quantifier Elimination via Functional Composition
|
Jie-Hong R. Jiang; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T07:43:11Z |
Symmetrization in Digital Circuit Optimization
|
JIE-HONG JIANG; Nina Yevtushenko; Natalia Eliseeva;Jie-Hong R. Jiang;Natalia Kushik;Nina Yevtushenko; Natalia Eliseeva; Jie-Hong R. Jiang; Natalia Kushik |
| 臺大學術典藏 |
2018-09-10T07:43:11Z |
Interpolating Functions from Large Boolean Relations
|
Jie-Hong R. Jiang;Hsuan-Po Lin;Wei-Lun Hung; Jie-Hong R. Jiang; Hsuan-Po Lin; Wei-Lun Hung; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T07:43:11Z |
Logic Synthesis in a Nutshell
|
Jie-Hong R. Jiang;Srinivas Devadas; Jie-Hong R. Jiang; Srinivas Devadas; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T07:43:11Z |
Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic
|
T.-T. Liu, L. Alarcón, M. Pierson,;J. Rabaey; T.-T. Liu, L. Alarcó; n, M. Pierson,; J. Rabaey; TSUNG-TE LIU |
| 臺大學術典藏 |
2018-09-10T07:43:12Z |
Commit Protocol for Lower-Powered Mobile Clients
|
Yen-Wen Lin; Hsiao-Kuang Wu; Feipei Lai; FEI-PEI LAI |
