臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:14:54Z	Image information splitting framework with importance sampling for robust transmission	Tsai, Chia-Liang;Chien, Shao-Yi; Tsai, Chia-Liang; Chien, Shao-Yi; SHAO-YI CHIEN
臺大學術典藏	2018-09-10T08:14:54Z	Efficient spatial-temporal error concealment algorithm and hardware architecture design for H.264/AVC	Wu, G.-L.;Chen, C.-Y.;Wu, T.-H.;Chien, S.-Y.; Wu, G.-L.; Chen, C.-Y.; Wu, T.-H.; Chien, S.-Y.; SHAO-YI CHIEN; Chen, Chien Chin; Chen, Ching-Yi
臺大學術典藏	2018-09-10T08:14:55Z	Direction-adaptive image upsampling using double interpolation	Lin, Y.-C.; Liu, Y.-N.; Chien, S.-Y.; Lin, Y.-C.; Liu, Y.-N.; Chien, S.-Y.; SHAO-YI CHIEN
臺大學術典藏	2018-09-10T08:14:55Z	Coarse-grained reconfigurable image stream processor architecture for high-definition cameras and camcorders	Cheng, T.-Y.;Chen, T.-H.;Chen, J.C.;Chien, S.-Y.; Cheng, T.-Y.; Chen, T.-H.; Chen, J.C.; Chien, S.-Y.; SHAO-YI CHIEN
臺大學術典藏	2018-09-10T08:14:55Z	Bandwidth adaptive hardware architecture of K-means clustering for video analysis	SHAO-YI CHIEN; Chien, S.-Y.; Chen, T.-W.; Chen, T.-W.;Chien, S.-Y.
臺大學術典藏	2018-09-10T08:14:55Z	Architecture design of fine grain quality scalable encoder with CABAC for H.264/AVC scalable extension	Chuang, T.-D.;Chen, Y.-J.;Chen, Y.-H.;Chien, S.-Y.;Chen, L.-G.; Chuang, T.-D.; Chen, Y.-J.; Chen, Y.-H.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN; SHAO-YI CHIEN
臺大學術典藏	2018-09-10T08:14:55Z	A multimedia semantic analysis SoC (SASoC) with machine-learning engine	Chen, T.-W.; Chen, Y.-L.; Cheng, T.-Y.; Tang, C.-S.; Tsung, P.-K.; Chuang, T.-D.; Chen, L.-G.; Chien, S.-Y.; LIANG-GEE CHEN; SHAO-YI CHIEN; Chen, T.-W.;Chen, Y.-L.;Cheng, T.-Y.;Tang, C.-S.;Tsung, P.-K.;Chuang, T.-D.;Chen, L.-G.;Chien, S.-Y.
臺大學術典藏	2018-09-10T08:14:56Z	A 212 MPixels/s 4096 × 2160p multiview video encoder chip for 3D/Quad full HDTV applications	SHAO-YI CHIEN; Chen, L.-G.; LIANG-GEE CHEN; Chien, S.-Y.; Chiu, H.-K.; Chen, Y.-H.; Chuang, T.-D.; Hsiao, P.-H.; Chen, W.-Y.; Tsung, P.-K.; Ding, L.-F.;Chen, W.-Y.;Tsung, P.-K.;Chuang, T.-D.;Hsiao, P.-H.;Chen, Y.-H.;Chiu, H.-K.;Chien, S.-Y.;Chen, L.-G.; Ding, L.-F.
臺大學術典藏	2018-09-10T08:14:56Z	Unified analytical global placement for large-scale mixed-size circuit designs	Hsu, M.-K.;Chang, Y.-W.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:56Z	Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis	Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG; Falkenstern, P.;Xie, Y.;Chang, Y.-W.;Wang, Y.
臺大學術典藏	2018-09-10T08:14:56Z	Template-mask design methodology for double patterning technology	Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:56Z	Redundant-wires-aware ECO timing and mask cost optimization	Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:56Z	Pulsed-latch aware placement for timing-integrity optimization	Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Predictive formulae for OPC with applications to lithography-friendly routing	Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Native-conflict-aware wire perturbation for double patterning technology	Chen, S.-Y.;Chang, Y.-W.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Multilayer global routing with via and wire capacity considerations	Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	ILP-based pin-count aware design methodology for microfluidic biochips	Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees	Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Fast timing-model independent buffered clock-tree synthesis	Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Efficient provably good OPC modeling and its applications to interconnect optimization	Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	ECO timing optimization using spare cells and technology remapping	Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Design-hierarchy aware mixed-size placement for routability optimization	Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Density gradient minimization with coupling-constrained dummy fill for CMP control	Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips	Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization	Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG

Showing items 1993501-1993525 of 2332647 (93306 Page(s) Totally)
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