| 臺大學術典藏 |
2018-09-10T14:57:27Z |
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS
|
Tai, H.-Y.;Tsai, C.-H.;Tsai, P.-Y.;Chen, H.-W.;Chen, H.-S.; Tai, H.-Y.; Tsai, C.-H.; Tsai, P.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立臺灣科技大學 |
2018 |
A 6-bit 1.3-GS/s ping-pong domino-SAR ADC in 55-nm CMOS
|
Chung Y.-H.; Rih W.-S.; Chang C.-W. |
| 國立臺灣科技大學 |
2018 |
A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS
|
Chung, Y.-H.;Rih, W.-S. |
| 臺大學術典藏 |
2004-08 |
A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
|
Chen, Yu-Hsun; Lee, Tai-Cheng; Chen, Yu-Hsun; Lee, Tai-Cheng |
| 國立臺灣大學 |
2004-08 |
A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
|
Chen, Yu-Hsun; Lee, Tai-Cheng |
| 國立臺灣大學 |
2007 |
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers
|
Shen, Ding-Lan; Lee, Tai-Cheng |
| 國立成功大學 |
2012-11 |
A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications
|
Chen, Ren-Li; Chang, Soon-Jyh |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification
|
Feng-Chiu Hsieh;Tai-Cheng; Feng-Chiu Hsieh; Tai-Cheng; TAI-CHENG LEE |
| 國立中山大學 |
2005-08 |
A 6-bit SAR pipelined ADC using improved TIQ technology
|
Yan-Huei Lee;Jyi-Tsong Lin |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 6-Gb/s Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuits
|
L-H Chiueh;T-C Lee; L-H Chiueh; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T09:25:30Z |
A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG)
|
C-D Su;C-W Lee;T-C Lee; C-D Su; C-W Lee; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:31:38Z |
A 6-GHz integer frequency synthesizer for SATA III applications in 0.18-μm CMOS technology
|
Cheng, J.-H.;Lin, J.-A.;Wu, M.-H.;Tsai, J.-H.;Huang, T.-W.; Cheng, J.-H.; Lin, J.-A.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator
|
C-H Wong;T-C Lee; C-H Wong; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:31:34Z |
A 6-GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA-III applications
|
Alsuraisry, H.;Cheng, J.-H.;Lin, J.-A.;Kuo, Y.-H.;Tsai, J.-H.;Huang, T.-W.; Alsuraisry, H.; Cheng, J.-H.; Lin, J.-A.; Kuo, Y.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:41:09Z |
A 6-GS/s, 6-bit, At-speed Testable ADC and DAC Pair in 0.13 mu m CMOS
|
Ho, Chen-Kang; Hong, Hao-Chiao |
| 國立臺灣大學 |
2008 |
A 6-Year Retrospective Epidemiologic Study of Pediatric Pneumococcal Pneumonia in Taiwan
|
黃懿娟; 何愉懷; 謝育嘉; 林曉娟; 黃高彬; 張鑾英; 黃立民; HUANG, YI-CHUAN; HO, YU-HUAI; HSIEH,YU- CHIA; LIN, HSIAO-CHUAN; HWANG, KAO-PIN; CHANG, LUAN-YIN; HUANG, LI-MIN |
| 國立臺灣大學 |
2008-12 |
A 6-year retrospective epidemiologic study of pediatric pneumococcal pneumonia in Taiwan
|
Huang, YC; Ho, YH; Hsieh, YC; Lin, HC; Hwang, KP; Chang, LY; Huang, LM |
| 臺大學術典藏 |
2020-12-15T07:42:23Z |
A 6-year retrospective epidemiologic study of pediatric pneumococcal pneumonia in Taiwan
|
Huang Y.-C.;Ho Y.-H.;Hsieh Y.-C.;Lin H.-C.;Hwang K.-P.;Luan-Yin Chang;Huang L.-M.; Huang Y.-C.; Ho Y.-H.; Hsieh Y.-C.; Lin H.-C.; Hwang K.-P.; LUAN-YIN CHANG; Huang L.-M. |
| 臺大學術典藏 |
2021-06-24T07:17:07Z |
A 6-year retrospective epidemiologic study of pediatric pneumococcal pneumonia in Taiwan
|
Huang Y.-C.; Ho Y.-H.; Hsieh Y.-C.; Lin H.-C.; Hwang K.-P.; Chang L.-Y.; LI-MIN HUANG |
| 中國醫藥大學 |
2008-04 |
A 6-year retrospective epidemiologic study of pediatric pneumococcal pneumonia in Taiwan.
|
黃懿娟(Yi-Chung Huang); 何瑜懷(Yu-Huai Ho); 謝高嘉(Yu-Chia Hsieh); 林曉娟(Hsiao-Chuan Lin); 黃高彬(Kao-Pin Hwang); 張巒英(Luan-Yin Chang); 黃立民(Li-Min Huang) |
| 國立臺灣大學 |
2005 |
A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver
|
Hsieh, Yong-Hsiang; Hu, Wei-Yi; Li, Wen-Kai; Lin, Shin-Ming; Chen, Chao-Liang; Chen, David J.; Chen, Sao-Jie |
| 臺大學術典藏 |
2018-09-10T04:53:33Z |
A 6.25mm2 2.4GHz CMOS 802.11b transceiver
|
Hsieh, Y.-H.; Hu, W.-Y.; Lin, S.-M.; Chang, J.; Chen, C.-L.; Li, W.-K.; Lo, C.-Y.; Chen, S.-J.; SAO-JIE CHEN |
| 國立中山大學 |
2002-05 |
A 6.4 Gbps FIFO Design for 8-32 two-way Data Exchange Bus
|
C.C. Wang;Y.H. Hsueh;Y.W. Chen |
| 臺大學術典藏 |
2021-03-12T08:40:59Z |
A 6.5/11/17.5/30-GHz high throughput interferometer-based reactance sensors using injection-locked oscillators and ping-pong nested chopping
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 臺大學術典藏 |
2021-03-12T08:41:00Z |
A 6.5/17.5-GHz dual-channel interferometer-based capacitive Sensor in 65-nm CMOS for high-speed flow cytometry
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
