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Taiwan Academic Institutional Repository >
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"顏金泰"
Showing items 11-20 of 100 (10 Page(s) Totally)
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| 中華大學 |
2012 |
Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Top-Down-Based Symmetrical Buffered Clock Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Direction-Constrained Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Timing-Constrained I/O Buffer Placement for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-Aware Length-Matching Bus Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance
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顏金泰; YAN, JIN-TAI |
Showing items 11-20 of 100 (10 Page(s) Totally)
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