臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

About TAIR
	About TAIR

Browse By
	Institution
	Author
	Title
	Date
	Statistics Chart
	Institution Facts
	Trend

News
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

Copyright
	Publisher & Journal Policy
	TAIR Copyright Conference Minutes

Related Links
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"顏金泰"

Return to Browse by Author
Sorting by Title	Sort by Date

Showing items 46-95 of 100 (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page

Institution	Date	Title	Author
中華大學	2008	Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits	顏金泰; YAN, JIN-TAI
中華大學	2008	Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids	顏金泰; YAN, JIN-TAI
中華大學	2008	Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance	顏金泰; YAN, JIN-TAI
中華大學	2008	Packing-Driven Sliceable Transformation for 3D Floorplan Designs	顏金泰; YAN, JIN-TAI
中華大學	2008	Noise-Aware Multiple-Voltage Assignment for gate-Level Power Optimization	顏金泰; YAN, JIN-TAI
中華大學	2008	Timing-Driven Steiner Tree Construction for Three-Dimensional ICs	顏金泰; YAN, JIN-TAI
中華大學	2008	Flexible Escape Routing for Flip-Chip Designs	顏金泰; YAN, JIN-TAI
中華大學	2007	Timing-Constrained Redundant Via Insertion for Yield Optimization	顏金泰; YAN, JIN-TAI
中華大學	2007	Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance	顏金泰; YAN, JIN-TAI
中華大學	2007	Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2007	Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis for Signal Integrity	顏金泰; YAN, JIN-TAI
中華大學	2007	Feasible Assignment of Wire-Bonding Power Pads in Hierarchical Power Quad-Grids for Signal Integrity	顏金泰; YAN, JIN-TAI
中華大學	2007	Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity	顏金泰; YAN, JIN-TAI
中華大學	2007	Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2007	Routability-Driven Track Routing for Coupling Capacitance Reduction	顏金泰; YAN, JIN-TAI
中華大學	2007	具有反面晶片技術的晶片與封裝共構繞線發展(I)	顏金泰
中華大學	2006	Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning	顏金泰; YAN, JIN-TAI
中華大學	2006	Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2006	Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment	顏金泰; YAN, JIN-TAI
中華大學	2006	Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis	顏金泰; YAN, JIN-TAI
中華大學	2006	Optimal Network Analysis in Hierarchical Power Quad-Grids	顏金泰; YAN, JIN-TAI
中華大學	2006	Width and Timing-Constrained Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2006	Multilevel Timing-Constrained Full-Chip Routing in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2006	Floorplan-Aware Decoupling Capacitance Budgeting on Equivalent Circuit Model	顏金泰; YAN, JIN-TAI
中華大學	2006	Area-Driven White Space Distribution for Detailed Floorplan Design	顏金泰; YAN, JIN-TAI
中華大學	2006	OPC-Aware Routing Reconstruction for OPE Reduction	顏金泰; YAN, JIN-TAI
中華大學	2006	Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
中華大學	2006	可避免干擾雜訊的SOC晶片繞線系統的開發	顏金泰
中華大學	2006	Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2005	Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Constrained Construction of Flexibility-Driven Routing Trees	顏金泰; YAN, JIN-TAI
中華大學	2005	Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Constrained Flexibility-Driven Routing Tree Construction	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points	顏金泰; YAN, JIN-TAI
中華大學	2005	Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids	顏金泰; YAN, JIN-TAI
中華大學	2005	Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation	顏金泰; YAN, JIN-TAI
中華大學	2005	Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2005	Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process	顏金泰; YAN, JIN-TAI
中華大學	2005	Timing-Driven Steiner Tree Construction with Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2005	LB-Packing-Based Floorplan Design on DBL Representation	顏金泰; YAN, JIN-TAI
中華大學	2005	Floorplan-Aware Steiner Tree Reconstruction for Optimal Buffer Insertion	顏金泰; YAN, JIN-TAI
中華大學	2005	Optimal Shielding Insertion for Inductive Noise Avoidance	顏金泰; YAN, JIN-TAI
中華大學	2005	具有訊號完整性的SOC晶片電源供應系統設計	顏金泰
中華大學	2004	Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
中華大學	2004	Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization	顏金泰; YAN, JIN-TAI
中華大學	2004	Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model	顏金泰; YAN, JIN-TAI
中華大學	2004	Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning	顏金泰; YAN, JIN-TAI
中華大學	2004	Double Bound List: A Dynamic Contour-Based Compacted Representation of Non-Slicing Floorplans on LB-Packing Solution Model	顏金泰; YAN, JIN-TAI
中華大學	2004	A Simulated-Annealing-Based Approach for Timing-Constrained Flexibility-Driven Routing Tree Construction	顏金泰; YAN, JIN-TAI
中華大學	2003	Optimal Wire Sizing for DME-Based Zero-Skew Clock Routing	顏金泰; YAN, JIN-TAI

Showing items 46-95 of 100 (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page

	English \| 正體中文 \| 简体中文 \| Total items :2853524
	Visitors : 45215992 Online Users : 921 Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library