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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"顏金泰"的相关文件
显示项目 46-55 / 100 (共10页) << < 1 2 3 4 5 6 7 8 9 10 > >> 每页显示[10|25|50]项目
| 中華大學 |
2008 |
Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Packing-Driven Sliceable Transformation for 3D Floorplan Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Noise-Aware Multiple-Voltage Assignment for gate-Level Power Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Steiner Tree Construction for Three-Dimensional ICs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Flexible Escape Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Redundant Via Insertion for Yield Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
显示项目 46-55 / 100 (共10页) << < 1 2 3 4 5 6 7 8 9 10 > >> 每页显示[10|25|50]项目
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