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"顏金泰"
Showing items 6-55 of 100 (2 Page(s) Totally)
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| 中華大學 |
2013 |
Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Resource-Constrained Link Insertion for Delay Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Utilization of Multi-Bit Flip-Flops for Clock Power Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Top-Down-Based Symmetrical Buffered Clock Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Direction-Constrained Layer Assignment for Rectangle Escape Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Timing-Constrained I/O Buffer Placement for Flip-Chip Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-Aware Length-Matching Bus Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Simultaneous Escape Routing Based on Routability-Driven Net Ordering
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
考量不同佈局需求的單層繞線系統開發
|
顏金泰 |
| 中華大學 |
2010 |
Thermal Via Planning for Temperature Reduction in 3D ICs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Low-Cost Low-Power Bypassing-Based Multiplier Design
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-Driven Flip-Flop Merging Process for Clock Power Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-driven partitioning-based IO assignment for flip-chip designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-Driven RDL Routing with Pin Reassignment
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Two-Sided Single-Detour Untangling for Bus Routing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Ordered Escape Routing via Routability-Driven Pin Assignment
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Width-constrained Wire Sizing for Non-tree Interconnections
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Resource-Constrained Timing-Driven Link Insertion for Critical Delay Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
在高密度印刷電路板設計下的匯流排導向繞線系統開發
|
顏金泰 |
| 中華大學 |
2009 |
Optimal Transformation of Non-tree Topologies for Timing Analysis
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Low-Power Multiplier Design with Row and Column Bypassing
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
RDL Pre-assignment Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Construction of Constrained Multi-Bit Flip-Flops for Clock Power Reduction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Accurate Transformation-Based Timing Analysis for RC Non-tree Circuits
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
Redundant Wire Insertion for Yield Improvement
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2009 |
考量溫度限制之三維晶片版面規劃與擺置系統開發
|
顏金泰 |
| 中華大學 |
2009 |
計算機組織與結構概論
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment and Path Reconstruction
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Constrained Yield-driven Redundant Via Insertion
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Thermal-Driven White Space Redistribution for Block-Level Floorplans
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Packing-Driven Sliceable Transformation for 3D Floorplan Designs
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Noise-Aware Multiple-Voltage Assignment for gate-Level Power Optimization
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Timing-Driven Steiner Tree Construction for Three-Dimensional ICs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2008 |
Flexible Escape Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Constrained Redundant Via Insertion for Yield Optimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
Showing items 6-55 of 100 (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page
|
