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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"顏金泰"的相關文件
顯示項目 6-30 / 100 (共4頁)
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每頁顯示[10|25|50]項目
| 中華大學 |
2013 |
Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Resource-Constrained Link Insertion for Delay Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Utilization of Multi-Bit Flip-Flops for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Top-Down-Based Symmetrical Buffered Clock Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2012 |
Direction-Constrained Layer Assignment for Rectangle Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
IO Connection Assignment and RDL Routing for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Timing-Constrained I/O Buffer Placement for Flip-Chip Designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
New Optimal Layer Assignment for Bus-Oriented Escape Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-Aware Length-Matching Bus Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
Simultaneous Escape Routing Based on Routability-Driven Net Ordering
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2011 |
考量不同佈局需求的單層繞線系統開發
|
顏金泰 |
| 中華大學 |
2010 |
Thermal Via Planning for Temperature Reduction in 3D ICs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Low-Cost Low-Power Bypassing-Based Multiplier Design
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-Driven Flip-Flop Merging Process for Clock Power Reduction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-driven partitioning-based IO assignment for flip-chip designs
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Routability-Driven RDL Routing with Pin Reassignment
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顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Two-Sided Single-Detour Untangling for Bus Routing
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Ordered Escape Routing via Routability-Driven Pin Assignment
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2010 |
Width-constrained Wire Sizing for Non-tree Interconnections
|
顏金泰; YAN, JIN-TAI |
顯示項目 6-30 / 100 (共4頁)
1 2 3 4 > >>
每頁顯示[10|25|50]項目
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