|
English
|
正體中文
|
简体中文
|
Total items :2853524
|
|
Visitors :
45207254
Online Users :
957
Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"顏金泰"
Showing items 76-85 of 100 (10 Page(s) Totally) << < 1 2 3 4 5 6 7 8 9 10 > >> View [10|25|50] records per page
| 中華大學 |
2005 |
Timing-Constrained Construction of Flexibility-Driven Routing Trees
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Constrained Flexibility-Driven Routing Tree Construction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction with Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
LB-Packing-Based Floorplan Design on DBL Representation
|
顏金泰; YAN, JIN-TAI |
Showing items 76-85 of 100 (10 Page(s) Totally) << < 1 2 3 4 5 6 7 8 9 10 > >> View [10|25|50] records per page
|