|
English
|
正體中文
|
简体中文
|
總筆數 :0
|
|
造訪人次 :
51260460
線上人數 :
831
教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
|
|
|
"顏金泰"的相關文件
顯示項目 76-85 / 100 (共10頁)
<< < 1 2 3 4 5 6 7 8 9 10 > >>
每頁顯示[10|25|50]項目
| 中華大學 |
2005 |
Timing-Constrained Construction of Flexibility-Driven Routing Trees
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Constrained Flexibility-Driven Routing Tree Construction
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
Timing-Driven Steiner Tree Construction with Buffer Insertion
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2005 |
LB-Packing-Based Floorplan Design on DBL Representation
|
顏金泰; YAN, JIN-TAI |
顯示項目 76-85 / 100 (共10頁)
<< < 1 2 3 4 5 6 7 8 9 10 > >>
每頁顯示[10|25|50]項目
|
