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"an yeu andy wu"的相关文件
显示项目 196-220 / 312 (共13页)
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| 臺大學術典藏 |
2018-09-10T08:15:38Z |
Cost-effective constrained particle filter for indoor localization
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Chao, C.-H.;Chu, C.-Y.;Chao, M.-A.;Wu, A.-Y.; Chao, C.-H.; Chu, C.-Y.; Chao, M.-A.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
Efficient parallelized particle filter design on CUDA
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Chao, M.-A.;Chu, C.-Y.;Chao, C.-H.;Wu, A.-Y.; Chao, M.-A.; Chu, C.-Y.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system
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Chen, Y.-L.;Jheng, T.-J.;Zhan, C.-Z.;Wu, A.-Y.; Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:01Z |
Scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem
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Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems
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Lin, S.-Y.;Shen, W.-C.;Hsu, C.-C.;Chao, C.-H.;Wu, A.-Y.; Lin, S.-Y.; Shen, W.-C.; Hsu, C.-C.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems
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AN-YEU(ANDY) WU; Wu, A.-Y.; Jheng, T.-J.; Chen, Y.-L.; Jheng, K.-Y.; Zhan, C.-Z.; Zhan, C.-Z.;Jheng, K.-Y.;Chen, Y.-L.;Jheng, T.-J.;Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
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Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; Tsai, T.-H.; AN-YEU(ANDY) WU; Lin, C.-H.;Chen, C.-Y.;Wu, A.-Y.;Tsai, T.-H. |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Multilevel LINC system designs for power efficiency enhancement of transmitters
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Jheng, K.-Y.;Chen, Y.-J.;Wu, A.-Y.; Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
PAC Duo SoC performance analysis with ESL design methodology
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Chuang, I.-Y.;Chang, C.-W.;Fan, T.-Y.;Yeh, J.-C.;Ji, K.-M.;Ma, J.-L.;Wu, A.-Y.;Lin, S.-Y.; Chuang, I.-Y.; Chang, C.-W.; Fan, T.-Y.; Yeh, J.-C.; Ji, K.-M.; Ma, J.-L.; Wu, A.-Y.; Lin, S.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:59Z |
A scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems
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Lin, S.-Y.;Hsu, C.-C.;Wu, A.-Y.; Lin, S.-Y.; Hsu, C.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:59Z |
A triple-mode LDPC decoder design for IEEE 802.11n system
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Chao, M.-A.;Wen, J.-Y.;Shih, X.-Y.;Wu, A.-Y.; Chao, M.-A.; Wen, J.-Y.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:58Z |
A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications
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AN-YEU(ANDY) WU; Wu, A.-Y.; Lin, C.-H.; Zhan, C.-Z.; Shih, X.-Y.; Shih, X.-Y.;Zhan, C.-Z.;Lin, C.-H.;Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T07:37:58Z |
A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices
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Shih, X.-Y.;Zhan, C.-Z.;Wu, A.-Y.; Shih, X.-Y.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:46Z |
Transform-domain delayed LMS algorithm and architecture
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Wu, An-Yeu; Wu, Cheng-Shing; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Algorithm-based low-power transform coding architectures: The multirate approach
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Wu, A.-Y.; Liu, K.J.R.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems
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Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology
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Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Fast algorithm for reduced-complexity programmable DSP implementation of the IFFT/FFT in DMT systems
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Wu, An-Yeu; Chan, Tsun-Shan; Wang, Bowen; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
Optimal fixed-point VLSI structure of a floating-point based digital filter design
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Wu, An-Yeu; Hwang, Kuo-Fuo; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:45Z |
System architecture of an adaptive reconfigurable DSP computing engine
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Wu, A.-Y.; Liu, K.J.R.; Raghupathy, A.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Overview of ITRI PAC project - From VLIW DSP processor to multicore computing platform
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AN-YEU(ANDY) WU; Wu, A.-Y.; Chu, Y.-H.; Lin, T.-J.; Liu, C.-N.; Tseng, S.-Y. |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-Balanced IP Mapping Algorithm for 2D-mesh on-chip-networks
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Lin, T.-J.; Lin, S.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Traffic-balanced routing algorithm for irregular mesh-based on-chip networks
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Lin, S.-Y.; Huang, C.-H.; Chao, C.-H.; Huang, K.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:44Z |
Algorithm-based low-power and high-performance multimedia signal processing
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Liu, K.J.R.; Wu, A.-Y.; Raghupathy, A.; Chen, J.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:04:43Z |
High-performance scheduling algorithm for partially parallel LDPC decoder
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Zhan, C.-Z.; Shih, X.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
显示项目 196-220 / 312 (共13页)
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