|
"an yeu andy wu"的相關文件
顯示項目 196-205 / 312 (共32頁)
<< < 15 16 17 18 19 20 21 22 23 24 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
Cost-effective constrained particle filter for indoor localization
|
Chao, C.-H.;Chu, C.-Y.;Chao, M.-A.;Wu, A.-Y.; Chao, C.-H.; Chu, C.-Y.; Chao, M.-A.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
Efficient parallelized particle filter design on CUDA
|
Chao, M.-A.;Chu, C.-Y.;Chao, C.-H.;Wu, A.-Y.; Chao, M.-A.; Chu, C.-Y.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T08:15:38Z |
A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system
|
Chen, Y.-L.;Jheng, T.-J.;Zhan, C.-Z.;Wu, A.-Y.; Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:01Z |
Scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem
|
Leu, Jye-Jong; Wu, An-Yeu; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems
|
Lin, S.-Y.;Shen, W.-C.;Hsu, C.-C.;Chao, C.-H.;Wu, A.-Y.; Lin, S.-Y.; Shen, W.-C.; Hsu, C.-C.; Chao, C.-H.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems
|
AN-YEU(ANDY) WU; Wu, A.-Y.; Jheng, T.-J.; Chen, Y.-L.; Jheng, K.-Y.; Zhan, C.-Z.; Zhan, C.-Z.;Jheng, K.-Y.;Chen, Y.-L.;Jheng, T.-J.;Wu, A.-Y. |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
|
Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; Tsai, T.-H.; AN-YEU(ANDY) WU; Lin, C.-H.;Chen, C.-Y.;Wu, A.-Y.;Tsai, T.-H. |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
Multilevel LINC system designs for power efficiency enhancement of transmitters
|
Jheng, K.-Y.;Chen, Y.-J.;Wu, A.-Y.; Jheng, K.-Y.; Chen, Y.-J.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:38:00Z |
PAC Duo SoC performance analysis with ESL design methodology
|
Chuang, I.-Y.;Chang, C.-W.;Fan, T.-Y.;Yeh, J.-C.;Ji, K.-M.;Ma, J.-L.;Wu, A.-Y.;Lin, S.-Y.; Chuang, I.-Y.; Chang, C.-W.; Fan, T.-Y.; Yeh, J.-C.; Ji, K.-M.; Ma, J.-L.; Wu, A.-Y.; Lin, S.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2018-09-10T07:37:59Z |
A scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems
|
Lin, S.-Y.;Hsu, C.-C.;Wu, A.-Y.; Lin, S.-Y.; Hsu, C.-C.; Wu, A.-Y.; AN-YEU(ANDY) WU |
顯示項目 196-205 / 312 (共32頁)
<< < 15 16 17 18 19 20 21 22 23 24 > >>
每頁顯示[10|25|50]項目
|
