| 臺大學術典藏 |
2018-09-10T15:00:42Z |
Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM Testing
|
B.C. Bai;C.A. Chen;J C.M Li; B.C. Bai; C.A. Chen; J C.M Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T15:00:42Z |
Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM Testing
|
B.C. Bai;C.A. Chen;J C.M Li; B.C. Bai; C.A. Chen; J C.M Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs
|
B. C. Bai;J. C. M. Li; B. C. Bai; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs
|
B. C. Bai;J. C. M. Li; B. C. Bai; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:07Z |
Power Scan: DFT for Power Switches in VLSI Designs
|
B. C. Bai; B. C. Bai; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:07Z |
Power Scan: DFT for Power Switches in VLSI Designs
|
B. C. Bai; B. C. Bai; CHIEN-MO LI |
