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Showing items 21-30 of 46 (5 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T15:33:16Z |
Factors governing phytoplankton biomass and production in tropical estuaries of western Taiwan
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Pan, C.-W.;Chuang, Y.-L.;Chou, L.-S.;Chen, M.-H.;Lin, H.-J.; Pan, C.-W.; Chuang, Y.-L.; Chou, L.-S.; Chen, M.-H.; Lin, H.-J.; LIEN-SIANG CHOU |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
Pulsed-latch aware placement for timing-integrity optimization
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Chuang, Y.-L.;Kim, S.;Shin, Y.;Chang, Y.-W.; Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs
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Chuang, Y.-L.;Lin, H.-T.;Ho, T.-Y.;Chang, Y.-W.;Marculescu, D.; Chuang, Y.-L.; Lin, H.-T.; Ho, T.-Y.; Chang, Y.-W.; Marculescu, D.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:36Z |
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
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Chuang, Y.-L.;Lee, P.-W.;Chang, Y.-W.; Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Design-hierarchy aware mixed-size placement for routability optimization
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Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Pulsed-latch aware placement for timing-integrity optimization
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Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:45:39Z |
Working hours and risk of gestational hypertension and pre-eclampsia
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Chang, P.-J.;Chu, L.-C.;Hsieh, W.-S.;Chuang, Y.-L.;Lin, S.-J.;Chen, P.-C.; Pau-Chung CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:53Z |
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
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Chuang, Y.-L.;Lee, P.-W.;Chang, Y.-W.; Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Effective wire models for X-architecture placement
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Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Constraint graph-based macro placement for modern mixed-size circuit designs
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Chen, H.-C.; Chuang, Y.-L.; Chang, Y.-W.; Chang, Y.-C.; YAO-WEN CHANG |
Showing items 21-30 of 46 (5 Page(s) Totally)
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