臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
國立交通大學	2014-12-12T01:19:21Z	提早載入：在深管線處理器設計下隱藏載入使用延遲	張順傑; Shun-Chieh Chang; 鍾崇斌; Chung-Ping Chung
國立交通大學	2014-12-12T01:13:18Z	藉由改變巨方塊中資料運算的順序以提升去方塊濾波器的效能	陳泰霖; Tai-Lin Chen; 鍾崇斌; Chung-Ping Chung
國立中山大學	2003	Data Item Placement for Load and Storage Balancing	Yung-Cheng Ma;Jih-Ching Chiu;Tien-Fu Chen;Chung-Ping Chung
國立中山大學	2002	Design of Instruction Address Queue for High Degree X86 Superscalar Architectures	Jih-Ching Chiu;Michael Jin-Yi Wang;Chung-Ping Chung
國立中山大學	2001	High-Bandwidth X86 Instruction Fetching Based on Instruction Pointer Table	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-12	The Fetch Mechanism Issue Of X86 Superscalar Processors with Fetch Rules	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-09	Design of instruction stream buffer with trace support for X86 processors	Jih-Ching Chiu;I-Huan Huang;Chung-Ping Chung
國立中山大學	1999-05	Survey of Instruction Fetch/Decode Unit and Data Load/Store Unit of X86 Superscalar Microprocessors	R-Ming Shiu;Jih-Ching Chiu;Yuh-Horng Shiau;Jean Jyh-Jiun Shann;Chung-Ping Chung
國立中山大學	1999-04	Design and Implementation of Instruction Fetch/Decode Unit and Data Load/Store Unit of X86 Superscalar Microprocessors	R-Ming Shiu;Jih-Ching Chiu;Yuh-Horng Shiau;Jean Jyh-Jiun Shann;Chung-Ping Chung
國立中山大學	1997-10	Instruction Cache Prefetching with Extended BTB	Shi-An Chi;R-Ming Shiu;Jih-Ching Chiu;Si-En Chang;Chung-Ping Chung

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