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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"chung ss"的相關文件
顯示項目 6-15 / 36 (共4頁)
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| 國立交通大學 |
2014-12-08T15:46:14Z |
A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:44:20Z |
New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistors
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Chung, SS; Chen, SJ; Yang, WJ; Yih, CM; Yang, JJ |
| 國立交通大學 |
2014-12-08T15:44:13Z |
Characterization of hot-hole injection induced SILC and related disturbs in flash memories
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Yih, CM; Ho, ZH; Liang, MS; Chung, SS |
| 國立交通大學 |
2014-12-08T15:27:48Z |
Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement results
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Chung, SS; Cheng, SM; Lee, GH; Guo, JC |
| 國立交通大學 |
2014-12-08T15:27:45Z |
Accurate MOS device hot carrier models for VLSI reliability simulation
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CHUNG, SS; YANG, JJ; SU, JS |
| 國立交通大學 |
2014-12-08T15:27:35Z |
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
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Yih, CM; Chung, SS; Hsu, CCH |
| 國立交通大學 |
2014-12-08T15:27:33Z |
A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation
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Chung, SS; Chen, DC; Cheng, CT; Yeh, CF |
| 國立交通大學 |
2014-12-08T15:27:25Z |
A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles
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Chung, SS; Yih, CM; Cheng, SM; Liang, MS |
| 國立交通大學 |
2014-12-08T15:27:23Z |
Performance and reliability evaluations of P-channel flash memories with different programming schemes
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Chung, SS; Kuo, SN; Yih, CM; Chao, TS |
| 國立交通大學 |
2014-12-08T15:27:09Z |
Universal switched-current integrator blocks for SI filter design
|
Chan, JL; Chung, SS |
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