| 國立交通大學 |
2018-08-21T05:57:09Z |
The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing Guidelines
|
Chung, Steve S.; Hsieh, E. R. |
| 國立交通大學 |
2018-08-21T05:57:09Z |
The Impact of TiN Barrier on the NBTI in an Advanced High-k Metal-gate p-channel MOSFET
|
Huang, D. -C.; Hsieh, E. Ray; Gong, J.; Huang, C. -F.; Chung, Steve S. |
| 國立交通大學 |
2018-08-21T05:57:00Z |
The Guideline on Designing Face-tunneling FET for Large-scale-device Applications in IoT
|
Hsieh, E. R.; Lee, J. W.; Lee, M. H.; Chung, Steve S. |
| 國立交通大學 |
2018-08-21T05:56:52Z |
A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance Applications
|
Hsieh, E. R.; Fan, Y. C.; Chang, K. Y.; Liu, C. H.; Chien, C. H.; Chung, Steve S. |
| 國立交通大學 |
2018-08-21T05:56:52Z |
Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs
|
Hsieh, E. R.; Fan, Y. C.; Liu, C. H.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2018-08-21T05:53:03Z |
A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
|
Hsieh, E. Ray; Kuo, Yen Chen; Cheng, Chih-Hung; Kuo, Jing Ling; Jiang, Meng-Ru; Lin, Jian-Li; Chen, Hung-Wen; Chung, Steve S.; Liu, Chuan-Hsi; Chen, Tse Pu; Huang, Shih An; Chen, Tai-Ju; Cheng, Osbert |
| 國立交通大學 |
2018-01-24T07:42:48Z |
新穎高性能鰭式電晶體結構 及其高頻特性分析
|
林建里; 莊紹勳; Lin, Jian-Li; Chung, Steve-S. |
| 國立交通大學 |
2018-01-24T07:42:00Z |
14奈米鰭式電晶體自熱效應的新穎溫度量測方法 及其對傳輸機制之影響
|
江孟儒; 莊紹勳; Jiang, Meng-Ru; Chung, Steve S. |
| 國立交通大學 |
2018-01-24T07:41:58Z |
一種新穎的鰭式電晶體可程式神經陣列 在人工神經網路的應用
|
陳泓文; 莊紹勳; Chen, Hung-Wen; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:56:06Z |
A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors
|
Hsieh, E. R.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:50:15Z |
Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm Scaling
|
Xu, Xiaoxin; Luo, Qing; Gong, Tiancheng; Lv, Hangbing; Long, Shibing; Liu, Qi; Chung, Steve S.; Li, Jing; Liu, Ming |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects
|
Hung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:50:15Z |
A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices
|
Hsieh, E. R.; Wang, Y. D.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Hsu, S. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
|
Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
The Process and Stress-Induced Variability Issues of Trigate CMOS Devices
|
Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:47Z |
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
|
Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:49:45Z |
3D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm Metal-Oxide-Semiconductor Field-Effect Transistor
|
Chou, Chen-Han; Hsu, Chung-Chun; Chung, Steve S.; Chien, Chao-Hsin |
| 國立交通大學 |
2017-04-21T06:49:45Z |
Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications
|
Hsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:28Z |
The Impact of the Three-Dimensional Gate on the Trigate FinFETs
|
Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:14Z |
A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
|
Hsieh, E. R.; Hung, C. M.; Wang, T. Y.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:49:09Z |
An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation
|
Hsieh, E. R.; Chuang, C. H.; Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:07Z |
Recent Advances of RTN Technique Towards the Understanding of the Gate Dielectric Reliability in Trigate FinFETs
|
Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:49:07Z |
Experimental Techniques on the Understanding of the Charge Loss in a SONOS Nitride-storage Nonvolatile Memory
|
Hsieh, E. R.; Wang, H. T.; Chung, Steve S.; Chang, Wayne; Wang, S. D.; Chen, C. H. |
| 國立交通大學 |
2017-04-21T06:49:02Z |
A Novel One Transistor Resistance-Gate Nonvolatile Memory
|
Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H. |
| 國立交通大學 |
2017-04-21T06:48:53Z |
The Random Dopant and Gate Oxide Variations in Trigate MOSFETs
|
Chung, Steve S. |
| 國立交通大學 |
2017-04-21T06:48:48Z |
3D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect Transistor
|
Chou, Chen-Han; Hsu, Chung-Chun; Yeh, Wen-Kuan; Chung, Steve S.; Chien, Chao-Hsin |
| 國立交通大學 |
2017-04-21T06:48:46Z |
A Novel One Transistor Non-volatile Memory Feasible for NOR and NAND Applications in IoT Era
|
Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H. |
| 國立交通大學 |
2017-04-21T06:48:32Z |
Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cells
|
Luo, Qing; Xu, Xiaoxin; Liu, Hongtao; Lv, Hangbing; Gong, Tiancheng; Long, Shibing; Liu, Qi; Sun, Haitao; Banerjee, Writam; Li, Ling; Gao, Jianfeng; Lu, Nianduan; Chung, Steve S.; Li, Jing; Liu, Ming |
| 國立交通大學 |
2017-04-21T06:48:18Z |
The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
|
Hsieh, E. R.; Huang, Z. H.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:48:17Z |
High Performance Design of Tunneling FET for Low Voltage/Power Applications: Strategies and Solutions
|
Chung, Steve S. |
| 國立交通大學 |
2016-03-29T00:01:14Z |
低功耗互補式穿隧場效電晶體的設計與製作 (I)
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T08:17:32Z |
高性能先進三維閘極CMOS應變元件設計-元件至電路的考量( III )
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T08:17:22Z |
低功耗互補式穿隧場效電晶體的設計與製作 (I)
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T00:04:19Z |
The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement
|
Hsieh, E. R.; Chung, Steve S. |
| 國立交通大學 |
2015-12-02T03:00:54Z |
The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
|
Wu, P. C.; Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T. |
| 國立交通大學 |
2015-12-02T02:59:13Z |
Impact of the TiN barrier layer on the positive bias temperature instabilities of high-k/metal-gate field effect transistors
|
Huang, Da-Cheng; Gong, Jeng; Huang, Chih-Fang; Chung, Steve S. |
| 國立交通大學 |
2015-11-26T01:07:58Z |
運用隨機電報訊號方法分析三閘極電晶體的多層級氧化層陷阱
|
蔡侑璉; Tsai, You-Lian; 莊紹勳; Chung, Steve S. |
| 國立交通大學 |
2015-11-26T01:06:42Z |
二氧化鉿電阻式記憶體多位元操作之隨機電報雜訊分析
|
黃英傑; Huang, Ying-Jie; 莊紹勳; Chung, Steve S. |
| 國立交通大學 |
2015-07-21T08:31:06Z |
Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Trigate MOSFETs and the Power Dissipation of SRAM
|
Hsieh, E. R.; Lin, S. T.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Jung, L. T. |
| 國立交通大學 |
2014-12-16T06:15:13Z |
Structure and process of basic complementary logic gate made by junctionless transistors
|
Chung Steve S.; Hsieh E. R. |
| 國立交通大學 |
2014-12-13T10:51:52Z |
張力型矽鍺奈米CMOS元件通道工程及可靠性關鍵問題研究(III)
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:51:36Z |
高速操作及高資料保存特性SONOS型式快閃記憶體之研究
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:51:21Z |
混合基片奈米CMOS元件技術中各種應力效應對傳輸特性及可靠性影響的研究
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:49:40Z |
下一世代高性能及高可靠性的N通道MOS元件設計及量測技術探討
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:49:26Z |
利用氘化及氮化處理製備高可靠性薄閘氧化層深次微米NMOS元件
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:49:24Z |
用於快閃式記憶元件及電路性能與可靠性模擬的元件模式
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:48:12Z |
混合基片奈米CMOS元件技術中各種應力效應對傳輸特性及可靠性影響的研究
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:48:01Z |
高性能先進三維閘極CMOS應變元件設計-元件至電路的考量 (II)
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:46:04Z |
奈米CMOS元件不均勻、雜和氧化層缺陷導致臨限電壓變異之研究(I)
|
莊紹勳; Chung Steve S |
| 國立交通大學 |
2014-12-13T10:45:16Z |
下一世代高性能及高可靠性的N通道MOS元件設計及量測技術探討
|
莊紹勳; Chung Steve S |
