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"chung steve s"的相關文件
顯示項目 41-50 / 136 (共14頁)
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| 國立交通大學 |
2017-04-21T06:48:48Z |
3D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect Transistor
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Chou, Chen-Han; Hsu, Chung-Chun; Yeh, Wen-Kuan; Chung, Steve S.; Chien, Chao-Hsin |
| 國立交通大學 |
2017-04-21T06:48:46Z |
A Novel One Transistor Non-volatile Memory Feasible for NOR and NAND Applications in IoT Era
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Chung, Steve S.; Hsieh, E. R.; Yang, S. P.; Chuang, C. H. |
| 國立交通大學 |
2017-04-21T06:48:32Z |
Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cells
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Luo, Qing; Xu, Xiaoxin; Liu, Hongtao; Lv, Hangbing; Gong, Tiancheng; Long, Shibing; Liu, Qi; Sun, Haitao; Banerjee, Writam; Li, Ling; Gao, Jianfeng; Lu, Nianduan; Chung, Steve S.; Li, Jing; Liu, Ming |
| 國立交通大學 |
2017-04-21T06:48:18Z |
The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
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Hsieh, E. R.; Huang, Z. H.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R. |
| 國立交通大學 |
2017-04-21T06:48:17Z |
High Performance Design of Tunneling FET for Low Voltage/Power Applications: Strategies and Solutions
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Chung, Steve S. |
| 國立交通大學 |
2016-03-29T00:01:14Z |
低功耗互補式穿隧場效電晶體的設計與製作 (I)
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莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T08:17:32Z |
高性能先進三維閘極CMOS應變元件設計-元件至電路的考量( III )
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莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T08:17:22Z |
低功耗互補式穿隧場效電晶體的設計與製作 (I)
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莊紹勳; Chung Steve S |
| 國立交通大學 |
2016-03-28T00:04:19Z |
The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement
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Hsieh, E. R.; Chung, Steve S. |
| 國立交通大學 |
2015-12-02T03:00:54Z |
The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
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Wu, P. C.; Hsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T. |
顯示項目 41-50 / 136 (共14頁)
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