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"jiang hc"的相關文件
顯示項目 1-15 / 15 (共1頁)
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| 國立交通大學 |
2019-04-02T06:04:42Z |
Active device under bond pad to save I/O layout for high-pin-count SOC
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Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:46:55Z |
A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector
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Jiang, HC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:46:30Z |
An improved BJT-based silicon retina with tunable image smoothing capability
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Wu, CY; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:43:54Z |
In the blink of a silicon eye
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Cheng, CH; Wu, CY; Sheu, B; Lin, LJ; Huang, KH; Jiang, HC; Yen, WC; Hsiao, CW |
| 國立交通大學 |
2014-12-08T15:43:10Z |
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
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Ker, MD; Jiang, HC; Chang, CY |
| 國立交通大學 |
2014-12-08T15:27:53Z |
AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS
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KER, MD; WU, CY; JIANG, HC; LEE, CY; KO, J; HSUE, P |
| 國立交通大學 |
2014-12-08T15:27:18Z |
The BJT-based silicon-retina sensory system for direction- and velocity-selective sensing
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Jiang, HC; Wu, CY |
| 國立交通大學 |
2014-12-08T15:27:06Z |
Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits
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Ker, MD; Jiang, HC; Chang, CY |
| 國立交通大學 |
2014-12-08T15:26:50Z |
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
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Ker, MD; Jiang, HC; Peng, JJ; Shieh, TL |
| 國立交通大學 |
2014-12-08T15:26:50Z |
ESD test methods on integrated circuits: An overview
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Ker, MD; Peng, JH; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:45Z |
Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology
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Ker, MD; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:38Z |
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
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Peng, JJ; Ker, MD; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:36Z |
Design of negative charge pump circuit with polysilicon diodes in a 0.25-mu m CMOS process
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Ker, MD; Chang, CY; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:28Z |
Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution
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Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:13Z |
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's
|
Ker, MD; Peng, JJ; Jiang, HC |
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