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"jiang i h r"的相关文件
显示项目 11-35 / 52 (共3页)
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| 臺大學術典藏 |
2020-06-11T06:12:59Z |
Feature detection for image analytics via FPGA acceleration
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Chang, H.-Y.;Jiang, I.H.-R.;Hofstee, H.P.;Jamsek, D.;Nam, G.-J.; Chang, H.-Y.; Jiang, I.H.-R.; Hofstee, H.P.; Jamsek, D.; Nam, G.-J.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:58Z |
OWARU: Free space-aware timing-driven incremental placement
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Reddy, L.; Jiang, I.H.-R.; Shin, Y.; HUI-RU JIANG; Jung, J.;Nam, G.-J.;Reddy, L.;Jiang, I.H.-R.;Shin, Y.; Jung, J.; Nam, G.-J. |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilog
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Cheng, A.-C.;Yen, C.-C.;Val, C.G.;Bayless, S.;Hu, A.J.;Jiang, I.H.-R.;Jou, J.-Y.; Cheng, A.-C.; Yen, C.-C.; Val, C.G.; Bayless, S.; Hu, A.J.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Analytical Clustering score with application to post-placement multi-bit flip-flop merging
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Xu, C.;Li, P.;Luo, G.;Shi, Y.;Jiang, I.H.-R.; Xu, C.; Li, P.; Luo, G.; Shi, Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Criticality-dependency-aware timing characterization and analysis
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Yang, Y.-M.;Tam, K.H.;Jiang, I.H.-R.; Yang, Y.-M.; Tam, K.H.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Functional ECO using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:56Z |
FF-bond: Multi-bit flip-flop bonding at placement
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Tsai, C.-C.;Shi, Y.;Luo, G.;Jiang, I.H.-R.; Tsai, C.-C.; Shi, Y.; Luo, G.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:56Z |
Machine-learning-based hotspot detection using topological classification and critical feature extraction
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Yu, Y.-T.;Lin, G.-H.;Jiang, I.H.-R.;Chiang, C.; Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:56Z |
PushPull: Short path padding for timing error resilient circuits
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Yang, Y.-M.;Jiang, I.H.-R.;Ho, S.-T.; Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:55Z |
Novel pulsed-latch replacement based on time borrowing and spiral clustering
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Chang, C.-L.;Jiang, I.H.-R.;Yang, Y.-M.;Tsai, E.Y.-W.;Chen, A.S.-H.; Chang, C.-L.; Jiang, I.H.-R.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, A.S.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
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Jiang, I.H.-R.;Chang, H.-Y.;Chang, C.-L.; Jiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs
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Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.;Tsai, E.Y.-W.;Chen, L.S.-F.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, L.S.-F.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
VIFI-CMP: Variability-tolerant chip-multiprocessors for throughput and power
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Lee, W.Y.;Jiang, I.H.-R.; Lee, W.Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
ECO optimization using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
PushPull: Short-path padding for timing error resilient circuits
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Yang, Y.-M.;Jiang, I.H.-R.;Ho, S.-T.; Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
Machine-learning-based hotspot detection using topological classification and critical feature extraction
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Yu, Y.-T.;Lin, G.-H.;Jiang, I.H.-R.;Chiang, C.; Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:51Z |
Pulsed-latch replacement using concurrent time borrowing and clock gating
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Chang, C.-L.;Jiang, I.H.-R.; Chang, C.-L.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:51Z |
INTEGRA: Fast multibit flip-flop clustering for clock power saving
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Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Recent research development in metal-only ECO
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Tan, C.-Y.;Jiang, I.H.-R.; Tan, C.-Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Generic integer linear programming formulation for 3D IC partitioning
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Jiang, I.H.-R.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Simultaneous voltage island generation and floorplanning
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Li, H.-Y.;Jiang, I.H.-R.;Chen, H.-M.; Li, H.-Y.; Jiang, I.H.-R.; Chen, H.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
Analog placement and global routing considering wiring symmetry
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Yang, Y.-M.;Jiang, I.H.-R.; Yang, Y.-M.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
3DICE: 3D IC cost evaluation based on fast tier number estimation
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Chan, C.-C.;Yu, Y.-T.;Jiang, I.H.-R.; Chan, C.-C.; Yu, Y.-T.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
Power-state-aware buffered tree construction
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Jiang, I.H.-R.;Wu, M.-H.; Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
POSA: Power-state-aware buffered tree construction
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Jiang, I.H.-R.;Wu, M.-H.; Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG |
显示项目 11-35 / 52 (共3页)
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