|
"jiang i h r"的相關文件
顯示項目 1-50 / 52 (共2頁)
1 2 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2021-09-02T00:09:07Z |
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:06Z |
Opportunities for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:05:12Z |
Opportunities for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:11Z |
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance
|
Huang X.-X;Chen H.-C;Wang S.-W;Jiang I.H.-R;Chou Y.-C;Tsai C.-H.; Huang X.-X; Chen H.-C; Wang S.-W; Jiang I.H.-R; Chou Y.-C; Tsai C.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:11Z |
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:11Z |
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design
|
Chen J;Jiang I.H.-R;Jung J;Kahng A.B;Kravets V.N;Li Y.-L;Lin S.-T;Woo M.; Chen J; Jiang I.H.-R; Jung J; Kahng A.B; Kravets V.N; Li Y.-L; Lin S.-T; Woo M.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:10Z |
A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles
|
Lin S.-C;Hsu H;Lin Y.-T;Lin C.-W;Jiang I.H.-R;Liu C.; Lin S.-C; Hsu H; Lin Y.-T; Lin C.-W; Jiang I.H.-R; Liu C.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:04:37Z |
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2021-09-02T00:04:37Z |
Opportunities for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:12:59Z |
Graph-based modeling, scheduling, and verification for intersection management of intelligent vehicles
|
Lin, Y.-T.;Hsu, H.;Lin, S.-C.;Lin, C.-W.;Jiang, I.H.-R.;Liu, C.; Lin, Y.-T.; Hsu, H.; Lin, S.-C.; Lin, C.-W.; Jiang, I.H.-R.; Liu, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:59Z |
Feature detection for image analytics via FPGA acceleration
|
Chang, H.-Y.;Jiang, I.H.-R.;Hofstee, H.P.;Jamsek, D.;Nam, G.-J.; Chang, H.-Y.; Jiang, I.H.-R.; Hofstee, H.P.; Jamsek, D.; Nam, G.-J.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:58Z |
OWARU: Free space-aware timing-driven incremental placement
|
Reddy, L.; Jiang, I.H.-R.; Shin, Y.; HUI-RU JIANG; Jung, J.;Nam, G.-J.;Reddy, L.;Jiang, I.H.-R.;Shin, Y.; Jung, J.; Nam, G.-J. |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilog
|
Cheng, A.-C.;Yen, C.-C.;Val, C.G.;Bayless, S.;Hu, A.J.;Jiang, I.H.-R.;Jou, J.-Y.; Cheng, A.-C.; Yen, C.-C.; Val, C.G.; Bayless, S.; Hu, A.J.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Analytical Clustering score with application to post-placement multi-bit flip-flop merging
|
Xu, C.;Li, P.;Luo, G.;Shi, Y.;Jiang, I.H.-R.; Xu, C.; Li, P.; Luo, G.; Shi, Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Criticality-dependency-aware timing characterization and analysis
|
Yang, Y.-M.;Tam, K.H.;Jiang, I.H.-R.; Yang, Y.-M.; Tam, K.H.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Functional ECO using metal-configurable gate-array spare cells
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:56Z |
FF-bond: Multi-bit flip-flop bonding at placement
|
Tsai, C.-C.;Shi, Y.;Luo, G.;Jiang, I.H.-R.; Tsai, C.-C.; Shi, Y.; Luo, G.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:56Z |
Machine-learning-based hotspot detection using topological classification and critical feature extraction
|
Yu, Y.-T.;Lin, G.-H.;Jiang, I.H.-R.;Chiang, C.; Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:56Z |
PushPull: Short path padding for timing error resilient circuits
|
Yang, Y.-M.;Jiang, I.H.-R.;Ho, S.-T.; Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:55Z |
Novel pulsed-latch replacement based on time borrowing and spiral clustering
|
Chang, C.-L.;Jiang, I.H.-R.;Yang, Y.-M.;Tsai, E.Y.-W.;Chen, A.S.-H.; Chang, C.-L.; Jiang, I.H.-R.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, A.S.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
|
Jiang, I.H.-R.;Chang, H.-Y.;Chang, C.-L.; Jiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs
|
Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.;Tsai, E.Y.-W.;Chen, L.S.-F.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, L.S.-F.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
VIFI-CMP: Variability-tolerant chip-multiprocessors for throughput and power
|
Lee, W.Y.;Jiang, I.H.-R.; Lee, W.Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
ECO optimization using metal-configurable gate-array spare cells
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
PushPull: Short-path padding for timing error resilient circuits
|
Yang, Y.-M.;Jiang, I.H.-R.;Ho, S.-T.; Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
Machine-learning-based hotspot detection using topological classification and critical feature extraction
|
Yu, Y.-T.;Lin, G.-H.;Jiang, I.H.-R.;Chiang, C.; Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:51Z |
Pulsed-latch replacement using concurrent time borrowing and clock gating
|
Chang, C.-L.;Jiang, I.H.-R.; Chang, C.-L.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:51Z |
INTEGRA: Fast multibit flip-flop clustering for clock power saving
|
Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Recent research development in metal-only ECO
|
Tan, C.-Y.;Jiang, I.H.-R.; Tan, C.-Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Generic integer linear programming formulation for 3D IC partitioning
|
Jiang, I.H.-R.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Simultaneous voltage island generation and floorplanning
|
Li, H.-Y.;Jiang, I.H.-R.;Chen, H.-M.; Li, H.-Y.; Jiang, I.H.-R.; Chen, H.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
Analog placement and global routing considering wiring symmetry
|
Yang, Y.-M.;Jiang, I.H.-R.; Yang, Y.-M.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
3DICE: 3D IC cost evaluation based on fast tier number estimation
|
Chan, C.-C.;Yu, Y.-T.;Jiang, I.H.-R.; Chan, C.-C.; Yu, Y.-T.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
Power-state-aware buffered tree construction
|
Jiang, I.H.-R.;Wu, M.-H.; Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
POSA: Power-state-aware buffered tree construction
|
Jiang, I.H.-R.;Wu, M.-H.; Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
Live demo: ECOS 1.0: A metal-only ECO synthesizer
|
Jiang, I.H.-R.;Chang, H.-Y.; Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
GasStation: Power and area efficient buffering for multiple power domain design
|
Lu, C.-P.;Jiang, I.H.-R.;Hsu, C.-H.; Lu, C.-P.; Jiang, I.H.-R.; Hsu, C.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations
|
Jiang, I.H.-R.;Nam, G.-J.;Chang, H.-Y.;Nassif, S.R.;Hayes, J.; Jiang, I.H.-R.; Nam, G.-J.; Chang, H.-Y.; Nassif, S.R.; Hayes, J.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
ITimerC: Common path pessimism removal using effective reduction methods
|
Yang, Y.-M.;Chang, Y.-W.;Jiang, I.H.-R.; Yang, Y.-M.; Chang, Y.-W.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
ITimerC 2.0: Fast incremental timing and CPPR analysis
|
Lee, P.-Y.;Jiang, I.H.-R.;Li, C.-R.;Chiu, W.-L.;Yang, Y.-M.; Lee, P.-Y.; Jiang, I.H.-R.; Li, C.-R.; Chiu, W.-L.; Yang, Y.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:46Z |
DRC-based hotspot detection considering edge tolerance and incomplete specification
|
Yu, Y.-T.;Jiang, I.H.-R.;Zhang, Y.;Chiang, C.; Yu, Y.-T.; Jiang, I.H.-R.; Zhang, Y.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:46Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:45Z |
FastPass: Fast timing path search for generalized timing exception handling
|
Lee, P.-Y.;Jiang, I.H.-R.;Chen, T.-C.HUI-RU JIANG;Chen, T.-C.;Jiang, I.H.-R.;Lee, P.-Y.; Lee, P.-Y.; Jiang, I.H.-R.; Chen, T.-C.; HUI-RU JIANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Functional ECO using metal-configurable gate-array spare cells
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
ECO optimization using metal-configurable gate-array spare cells
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
|
Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization using metal-configurable gate-array spare cells
|
Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
Simultaneous functional and timing ECO
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:36Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Reliable crosstalk-driven interconnect optimization
|
Jiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG |
顯示項目 1-50 / 52 (共2頁)
1 2 > >>
每頁顯示[10|25|50]項目
|
