|
|
???tair.name??? >
???browser.page.title.author???
|
"jiang i h r"???jsp.browse.items-by-author.description???
Showing items 21-45 of 52 (3 Page(s) Totally)
1 2 3 > >>
View [10|25|50] records per page
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
|
Jiang, I.H.-R.;Chang, H.-Y.;Chang, C.-L.; Jiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs
|
Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.;Tsai, E.Y.-W.;Chen, L.S.-F.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, L.S.-F.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
VIFI-CMP: Variability-tolerant chip-multiprocessors for throughput and power
|
Lee, W.Y.;Jiang, I.H.-R.; Lee, W.Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
ECO optimization using metal-configurable gate-array spare cells
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
PushPull: Short-path padding for timing error resilient circuits
|
Yang, Y.-M.;Jiang, I.H.-R.;Ho, S.-T.; Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
Machine-learning-based hotspot detection using topological classification and critical feature extraction
|
Yu, Y.-T.;Lin, G.-H.;Jiang, I.H.-R.;Chiang, C.; Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:51Z |
Pulsed-latch replacement using concurrent time borrowing and clock gating
|
Chang, C.-L.;Jiang, I.H.-R.; Chang, C.-L.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:51Z |
INTEGRA: Fast multibit flip-flop clustering for clock power saving
|
Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Recent research development in metal-only ECO
|
Tan, C.-Y.;Jiang, I.H.-R.; Tan, C.-Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Generic integer linear programming formulation for 3D IC partitioning
|
Jiang, I.H.-R.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Simultaneous voltage island generation and floorplanning
|
Li, H.-Y.;Jiang, I.H.-R.;Chen, H.-M.; Li, H.-Y.; Jiang, I.H.-R.; Chen, H.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
Analog placement and global routing considering wiring symmetry
|
Yang, Y.-M.;Jiang, I.H.-R.; Yang, Y.-M.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
3DICE: 3D IC cost evaluation based on fast tier number estimation
|
Chan, C.-C.;Yu, Y.-T.;Jiang, I.H.-R.; Chan, C.-C.; Yu, Y.-T.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
Power-state-aware buffered tree construction
|
Jiang, I.H.-R.;Wu, M.-H.; Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
POSA: Power-state-aware buffered tree construction
|
Jiang, I.H.-R.;Wu, M.-H.; Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:48Z |
Live demo: ECOS 1.0: A metal-only ECO synthesizer
|
Jiang, I.H.-R.;Chang, H.-Y.; Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
GasStation: Power and area efficient buffering for multiple power domain design
|
Lu, C.-P.;Jiang, I.H.-R.;Hsu, C.-H.; Lu, C.-P.; Jiang, I.H.-R.; Hsu, C.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations
|
Jiang, I.H.-R.;Nam, G.-J.;Chang, H.-Y.;Nassif, S.R.;Hayes, J.; Jiang, I.H.-R.; Nam, G.-J.; Chang, H.-Y.; Nassif, S.R.; Hayes, J.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
ITimerC: Common path pessimism removal using effective reduction methods
|
Yang, Y.-M.;Chang, Y.-W.;Jiang, I.H.-R.; Yang, Y.-M.; Chang, Y.-W.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
ITimerC 2.0: Fast incremental timing and CPPR analysis
|
Lee, P.-Y.;Jiang, I.H.-R.;Li, C.-R.;Chiu, W.-L.;Yang, Y.-M.; Lee, P.-Y.; Jiang, I.H.-R.; Li, C.-R.; Chiu, W.-L.; Yang, Y.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:46Z |
DRC-based hotspot detection considering edge tolerance and incomplete specification
|
Yu, Y.-T.;Jiang, I.H.-R.;Zhang, Y.;Chiang, C.; Yu, Y.-T.; Jiang, I.H.-R.; Zhang, Y.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:46Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:45Z |
FastPass: Fast timing path search for generalized timing exception handling
|
Lee, P.-Y.;Jiang, I.H.-R.;Chen, T.-C.HUI-RU JIANG;Chen, T.-C.;Jiang, I.H.-R.;Lee, P.-Y.; Lee, P.-Y.; Jiang, I.H.-R.; Chen, T.-C.; HUI-RU JIANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Functional ECO using metal-configurable gate-array spare cells
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
ECO optimization using metal-configurable gate-array spare cells
|
Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
Showing items 21-45 of 52 (3 Page(s) Totally)
1 2 3 > >>
View [10|25|50] records per page
|
