| 國立交通大學 |
2014-12-08T15:23:44Z |
POSA: Power-State-Aware Buffered Tree Construction
|
Jiang, Iris Hui-Ru; Wu, Ming-Hua |
| 國立交通大學 |
2014-12-08T15:23:14Z |
GENERIC INTEGER LINEAR PROGRAMMING FORMULATION FOR 3D IC PARTITIONING
|
Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:23:05Z |
Novel Pulsed-Latch Replacement Based on Time Borrowing and Spiral Clustering
|
Chang, Chih-Long; Jiang, Iris Hui-Ru; Yang, Yu-Ming; Tsai, Evan Yu-Wen; Chen, Aki Sheng-Hua |
| 國立交通大學 |
2014-12-08T15:22:17Z |
WiT: Optimal Wiring Topology for Electromigration Avoidance
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Chih-Long |
| 國立交通大學 |
2014-12-08T15:22:06Z |
Reliability-Driven Power/Ground Routing for Analog ICs
|
Lin, Jing-Wei; Ho, Tsung-Yi; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:21:55Z |
ECOS: Stable Matching Based Metal-Only ECO Synthesis
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu |
| 國立交通大學 |
2014-12-08T15:21:26Z |
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
|
Jiang, Iris Hui-Ru; Chang, Chih-Long; Yang, Yu-Ming |
| 國立交通大學 |
2014-12-08T15:21:18Z |
3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
|
Chan, Cheng-Chi; Yu, Yen-Ting; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:20:29Z |
Recent Research Development in Metal-Only ECO
|
Tan, Chuan-Yao; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:19:35Z |
VIFI-CMP: Variability-Tolerant Chip-Multiprocessors for Throughput and Power
|
Lee, Wan-Yu; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:19:20Z |
Matching-Based Minimum-Cost Spare Cell Selection for Design Changes
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Liang-Gi; Hung, Huang-Bi |
| 國立交通大學 |
2014-12-08T15:04:51Z |
Topology generation and floorplanning for low power application-specific Network-on-Chips
|
Lee, Wan-Yu; Jiang, Iris Hui-Ru |
| 國立成功大學 |
2012-01 |
Reliability-Driven Power/Ground Routing for Analog ICs
|
Lin, Jing-Wei; Ho, Tsung-Yi; Jiang, Iris Hui-Ru |
| 國立臺灣大學 |
2006 |
Reliable crosstalk-driven interconnect optimization
|
Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
| 臺大學術典藏 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan; Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
| 國立臺灣大學 |
2000 |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang |
