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Taiwan Academic Institutional Repository >
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"jiang iris hui ru"
Showing items 81-90 of 92 (10 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:21:55Z |
ECOS: Stable Matching Based Metal-Only ECO Synthesis
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Jiang, Iris Hui-Ru; Chang, Hua-Yu |
| 國立交通大學 |
2014-12-08T15:21:26Z |
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
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Jiang, Iris Hui-Ru; Chang, Chih-Long; Yang, Yu-Ming |
| 國立交通大學 |
2014-12-08T15:21:18Z |
3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
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Chan, Cheng-Chi; Yu, Yen-Ting; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:20:29Z |
Recent Research Development in Metal-Only ECO
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Tan, Chuan-Yao; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:19:35Z |
VIFI-CMP: Variability-Tolerant Chip-Multiprocessors for Throughput and Power
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Lee, Wan-Yu; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:19:20Z |
Matching-Based Minimum-Cost Spare Cell Selection for Design Changes
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Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Liang-Gi; Hung, Huang-Bi |
| 國立交通大學 |
2014-12-08T15:04:51Z |
Topology generation and floorplanning for low power application-specific Network-on-Chips
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Lee, Wan-Yu; Jiang, Iris Hui-Ru |
| 國立成功大學 |
2012-01 |
Reliability-Driven Power/Ground Routing for Analog ICs
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Lin, Jing-Wei; Ho, Tsung-Yi; Jiang, Iris Hui-Ru |
| 國立臺灣大學 |
2006 |
Reliable crosstalk-driven interconnect optimization
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Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
Showing items 81-90 of 92 (10 Page(s) Totally)
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