| 臺大學術典藏 |
2020-06-16T06:31:36Z |
Simultaneous functional and timing ECO.
|
Chang, Hua-Yu;Jiang, Iris Hui-Ru;Chang, Yao-Wen; Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2020-06-11T06:12:55Z |
Simultaneous functional and timing ECO.
|
Chang, Hua-Yu;Jiang, Iris Hui-Ru;Chang, Yao-Wen; Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
Matching-based minimum-cost spare cell selection for design changes.
|
Jiang, Iris Hui-Ru;Chang, Hua-Yu;Chang, Liang-Gi;Hung, Huang-Bi; Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Liang-Gi; Hung, Huang-Bi; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
Timing Macro Modeling for Efficient Hierarchical Timing Analysis.
|
Jiang, Iris Hui-Ru;Lee, Pei-Yu; Jiang, Iris Hui-Ru; Lee, Pei-Yu; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
The overview of 2014 CAD contest at ICCAD.
|
Jiang, Iris Hui-Ru;Viswanathan, Natarajan;Chen, Tai-Chen;Li, Jin-Fu; Jiang, Iris Hui-Ru; Viswanathan, Natarajan; Chen, Tai-Chen; Li, Jin-Fu; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:46Z |
The overview of 2013 CAD contest at ICCAD.
|
Jiang, Iris Hui-Ru;Li, Zhuo;Wang, Hwei-Tseng;Viswanathan, Natarajan; Jiang, Iris Hui-Ru; Li, Zhuo; Wang, Hwei-Tseng; Viswanathan, Natarajan; HUI-RU JIANG |
| 國立交通大學 |
2020-05-05T00:02:00Z |
DATC RDF-2019: Towards a Complete Academic Reference Design Flow
|
Lin, Shih-Ting; Woo, Mingyu; Li, Yih-Lang; Jiang, Iris Hui-Ru; Jung, Jinwook; Kahng, Andrew B.; Kravets, Victor N.; Chen, Jianli |
| 臺大學術典藏 |
2020-05-04T07:53:49Z |
Graph-Based Modeling, Scheduling, and Verification for Intersection Management of Intelligent Vehicles.
|
Lin, Chung-Wei; Jiang, Iris Hui-Ru; Liu, Changliu; CHUNG-WEI LIN; Lin, Shang-Chien; Hsu, Hsiang; Lin, Yi-Ting; Lin, Yi-Ting;Hsu, Hsiang;Lin, Shang-Chien;Lin, Chung-Wei;Jiang, Iris Hui-Ru;Liu, Changliu |
| 國立交通大學 |
2019-12-13T01:12:53Z |
DATC RDF: An Academic Flow from Logic Synthesis to Detailed Routing
|
Jung, Jinwook; Jiang, Iris Hui-Ru; Chen, Jianli; Lin, Shih-Ting; Li, Yih-Lang; Kravets, Victor N.; Nam, Gi-Joon |
| 國立交通大學 |
2019-08-02T02:14:47Z |
Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing
|
Chang, Ya-Chu; Lin, Tung-Wei; Jiang, Iris Hui-Ru; Nam, Gi-Joon |
| 國立交通大學 |
2019-04-02T06:04:30Z |
Timing Macro Modeling for Efficient Hierarchical Timing Analysis
|
Jiang, Iris Hui-Ru; Lee, Pei-Yu |
| 國立交通大學 |
2019-04-02T06:00:44Z |
iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis
|
Lee, Pei-Yu; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2019-01-01 |
Efficient Search of Layout Hotspot Patterns for Matching SEM Images using Multilevel Pixelation
|
Chang, Wei-Chun; Jiang, Iris Hui-Ru; Zhu, Jun; Shiely, James P.; Tseng, Sean Shang-En |
| 臺大學術典藏 |
2018-09-10T07:36:58Z |
Clustering- and probability-based approach for time-multiplexed FPGA partitioning
|
Chang, Yao-Wen; YAO-WEN CHANG; Jiang, Iris Hui-Ru; Chao, Mango Chia-Tso; Wu, Guang-Ming |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Optimal reliable crosstalk-driven interconnect optimization
|
Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG |
| 國立交通大學 |
2018-08-21T05:57:09Z |
FastPass: Fast Timing Path Search for Generalized Timing Exception Handling
|
Lee, Pei-Yu; Jiang, Iris Hui-Ru; Chen, Tung-Chieh |
| 國立交通大學 |
2018-08-21T05:57:00Z |
Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation
|
Chiu, Wei-Lun; Jiang, Iris Hui-Ru; Lu, Chien-Pang; Chang, Yu-Tung |
| 國立交通大學 |
2018-08-21T05:57:00Z |
iClaire: A Fast and General Layout Pattern Classification Algorithm
|
Chang, Wei-Chun; Jiang, Iris Hui-Ru; Yu, Yen-Ting; Liu, Wei-Fang |
| 國立交通大學 |
2018-08-21T05:56:59Z |
DATC RDF: Robust Design Flow Database
|
Jung, Jinwook; Lee, Pei-Yu; Wu, Yan-Shiun; Darav, Nima Karimpour; Jiang, Iris Hui-Ru; Kravets, Victor N.; Behjat, Laleh; Li, Yih-Lang; Nam, Gi-Joon |
| 國立交通大學 |
2018-08-21T05:56:49Z |
Fast Low Power Rule Checking for Multiple Power Domain Design
|
Lu, Chien-Pang; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2018-08-21T05:56:32Z |
Simultaneous Functional and Timing ECO
|
Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen |
| 國立交通大學 |
2017-04-21T06:55:43Z |
Analytical Clustering Score with Application to Postplacement Register Clustering
|
Xu, Chang; Luo, Guojie; Li, Peixin; Shi, Yiyu; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2017-04-21T06:50:17Z |
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules
|
Chang, Hua-Yu; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2017-04-21T06:50:17Z |
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules
|
Chang, Hua-Yu; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2017-04-21T06:50:13Z |
iTimerC: Common Path Pessimism Removal Using Effective Reduction Methods
|
Yang, Yu-Ming; Chang, Yu-Wei; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2017-04-21T06:50:13Z |
Smart Grid Load Balancing Techniques via Simultaneous Switch/Tie-line/Wire Configurations
|
Jiang, Iris Hui-Ru; Nam, Gi-Joon; Chang, Hua-Yu; Nassif, Sani R.; Hayes, Jerry |
| 國立交通大學 |
2017-04-21T06:50:12Z |
The Overview of 2014 CAD Contest at ICCAD Special Session Paper: CAD Contest
|
Jiang, Iris Hui-Ru; Viswanathan, Natarajan; Chen, Tai-Chen; Li, Jin-Fu |
| 國立交通大學 |
2017-04-21T06:50:11Z |
DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification
|
Yu, Yen-Ting; Jiang, Iris Hui-Ru; Zhang, Yumin; Chiang, Charles |
| 國立交通大學 |
2017-04-21T06:50:08Z |
OpenDesign Flow Database: The Infrastructure for VLSI Design and Design Automation Research
|
Jung, Jinwook; Jiang, Iris Hui-Ru; Nam, Gi-Joon; Kravets, Victor N.; Behjat, Laleh; Li, Yih-Lang |
| 國立交通大學 |
2017-04-21T06:50:08Z |
OWARU: Free Space-Aware Timing-Driven Incremental Placement
|
Jung, Jinwook; Nam, Gi-Joon; Reddy, Lakshmi; Jiang, Iris Hui-Ru; Shin, Youngsoo |
| 國立交通大學 |
2017-04-21T06:50:07Z |
Timing ECO Optimization via Bezier Curve Smoothing and Fixability Identification
|
Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen |
| 國立交通大學 |
2017-04-21T06:49:52Z |
Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits
|
Schlichtmann, Ulf; Hashimoto, Masanori; Jiang, Iris Hui-Ru; Li, Bing |
| 國立交通大學 |
2017-04-21T06:49:29Z |
Resource-Aware Functional ECO Patch Generation
|
Cheng, An-Che; Jiang, Iris Hui-Ru; Jou, Jing-Yang |
| 國立交通大學 |
2017-04-21T06:49:13Z |
Criticality-Dependency-Aware Timing Characterization and Analysis
|
Yang, Yu-Ming; Tam, King Ho; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2017-04-21T06:48:45Z |
Functional ECO Using Metal-Configurable Gate-Array Spare Cells
|
Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen |
| 國立交通大學 |
2017-04-21T06:48:38Z |
Analog Placement and Global Routing Considering Wiring Symmetry
|
Yang, Yu-Ming; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2016-03-29T00:01:06Z |
新興電子設計自動化之應用：一個智慧型配電網路最佳化平台
|
江蕙如; Jiang Iris Hui-Ru |
| 國立交通大學 |
2016-03-28T08:17:51Z |
新興電子設計自動化之應用：一個智慧型配電網路最佳化平台
|
江蕙如; Jiang Iris Hui-Ru |
| 國立交通大學 |
2016-03-28T00:05:45Z |
GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design
|
Lu, Chien-Pang; Jiang, Iris Hui-Ru; Hsu, Chin-Hsiung |
| 國立交通大學 |
2016-03-28T00:05:45Z |
iTimerC 2.0: Fast Incremental Timing and CPPR Analysis
|
Lee, Pei-Yu; Jiang, Iris Hui-Ru; Li, Cheng-Ruei; Chiu, Wei-Lun; Yang, Yu-Ming |
| 國立交通大學 |
2015-11-26T00:55:31Z |
針對奈米積體電路之時序分析與最佳化
|
楊喻名; Yang, Yu-Ming; 江蕙如; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2015-07-21T11:21:09Z |
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
|
Cheng, An-Che; Yen, Chia-Chih (Jack); Val, Celina G.; Bayless, Sam; Hu, Alan J.; Jiang, Iris Hui-Ru; Jou, Jing-Yang |
| 國立交通大學 |
2015-07-21T08:29:41Z |
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
|
Yu, Yen-Ting; Lin, Geng-He; Jiang, Iris Hui-Ru; Chiang, Charles |
| 國立交通大學 |
2014-12-16T06:15:20Z |
METHOD FOR ANALOG PLACEMENT AND GLOBAL ROUTING CONSIDERING WIRING SYMMETRY
|
JIANG Iris Hui-Ru; YANG Yu-Ming |
| 國立交通大學 |
2014-12-16T06:14:09Z |
Method for analog placement and global routing considering wiring symmetry
|
Jiang Iris Hui-Ru; Yang Yu-Ming |
| 國立交通大學 |
2014-12-13T10:51:51Z |
單晶片系統驗證之核心技術開發---子計畫四：單晶片系統設計流程之實體驗證(III)
|
江蕙如; Jiang Iris Hui-Ru |
| 國立交通大學 |
2014-12-13T10:51:11Z |
後次微米時代新興電子設計自動化技術之研究----子計畫二：整合性低耗電管理之技術開發(I)
|
江蕙如; Jiang Iris Hui-Ru |
| 國立交通大學 |
2014-12-13T10:48:43Z |
後次微米時代新興電子設計自動化技術之研究---子計畫二：整合性低耗電管理之技術開發(II)
|
江蕙如; Jiang Iris Hui-Ru |
| 國立交通大學 |
2014-12-13T10:48:01Z |
新興電子設計自動化之應用：一個智慧型配電網路最佳化平台
|
江蕙如; Jiang Iris Hui-Ru |
