| 國立交通大學 |
2014-12-08T15:45:55Z |
UNIFICATION OF OBSTACLE-AVOIDING RECTILINEAR STEINER TREE CONSTRUCTION
|
Jiang, Iris Hui-Ru; Lin, Shung-Wei; Yu, Yen-Ting |
| 國立交通大學 |
2014-12-08T15:38:42Z |
Live Demo: ECOS 1.0: A Metal-Only ECO Synthesizer
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu |
| 國立交通大學 |
2014-12-08T15:36:24Z |
PushPull: Short-Path Padding for Timing Error Resilient Circuits
|
Yang, Yu-Ming; Jiang, Iris Hui-Ru; Ho, Sung-Ting |
| 國立交通大學 |
2014-12-08T15:34:50Z |
The Overview of 2013 CAD Contest at ICCAD
|
Jiang, Iris Hui-Ru; Li, Zhuo; Wang, Hwei-Tseng; Viswanathan, Natarajan |
| 國立交通大學 |
2014-12-08T15:33:12Z |
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
|
Yu, Yen-Ting; Lin, Geng-He; Jiang, Iris Hui-Ru; Chiang, Charles |
| 國立交通大學 |
2014-12-08T15:30:08Z |
Opening: Introduction to CAD Contest at ICCAD 2012 CAD Contest
|
Jiang, Iris Hui-Ru; Li, Zhuo; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:29:33Z |
Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating
|
Chang, Chih-Long; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:28:32Z |
Generic Integer Linear Programming Formulation for 3D IC Partitioning
|
Lee, Wan-Yu; Jiang, Iris Hui-Ru; Mei, Tsung-Wan |
| 國立交通大學 |
2014-12-08T15:28:29Z |
Timing ECO Optimization Via Bezier Curve Smoothing and Fixability Identification
|
Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen |
| 國立交通大學 |
2014-12-08T15:28:24Z |
Accurate Process-Hotspot Detection Using Critical Design Rule Extraction
|
Yu, Yen-Ting; Chan, Ya-Chung; Sinha, Subarna; Jiang, Iris Hui-Ru; Chiang, Charles |
| 國立交通大學 |
2014-12-08T15:23:44Z |
POSA: Power-State-Aware Buffered Tree Construction
|
Jiang, Iris Hui-Ru; Wu, Ming-Hua |
| 國立交通大學 |
2014-12-08T15:23:14Z |
GENERIC INTEGER LINEAR PROGRAMMING FORMULATION FOR 3D IC PARTITIONING
|
Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:23:05Z |
Novel Pulsed-Latch Replacement Based on Time Borrowing and Spiral Clustering
|
Chang, Chih-Long; Jiang, Iris Hui-Ru; Yang, Yu-Ming; Tsai, Evan Yu-Wen; Chen, Aki Sheng-Hua |
| 國立交通大學 |
2014-12-08T15:22:17Z |
WiT: Optimal Wiring Topology for Electromigration Avoidance
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Chih-Long |
| 國立交通大學 |
2014-12-08T15:22:06Z |
Reliability-Driven Power/Ground Routing for Analog ICs
|
Lin, Jing-Wei; Ho, Tsung-Yi; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:21:55Z |
ECOS: Stable Matching Based Metal-Only ECO Synthesis
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu |
| 國立交通大學 |
2014-12-08T15:21:26Z |
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
|
Jiang, Iris Hui-Ru; Chang, Chih-Long; Yang, Yu-Ming |
| 國立交通大學 |
2014-12-08T15:21:18Z |
3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
|
Chan, Cheng-Chi; Yu, Yen-Ting; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:20:29Z |
Recent Research Development in Metal-Only ECO
|
Tan, Chuan-Yao; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:19:35Z |
VIFI-CMP: Variability-Tolerant Chip-Multiprocessors for Throughput and Power
|
Lee, Wan-Yu; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:19:20Z |
Matching-Based Minimum-Cost Spare Cell Selection for Design Changes
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Liang-Gi; Hung, Huang-Bi |
| 國立交通大學 |
2014-12-08T15:04:51Z |
Topology generation and floorplanning for low power application-specific Network-on-Chips
|
Lee, Wan-Yu; Jiang, Iris Hui-Ru |
| 國立成功大學 |
2012-01 |
Reliability-Driven Power/Ground Routing for Analog ICs
|
Lin, Jing-Wei; Ho, Tsung-Yi; Jiang, Iris Hui-Ru |
| 國立臺灣大學 |
2006 |
Reliable crosstalk-driven interconnect optimization
|
Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
