臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

	English \| 正體中文 \| 简体中文 \| Total items :0
	Visitors : 51242839 Online Users : 680 Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library

Scope

Adv. Search

Login

Administrator

臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

About TAIR
	About TAIR

Browse By
	Institution
	Author
	Title
	Date
	Statistics Chart
	Institution Facts
	Trend

News
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

Copyright
	Publisher & Journal Policy
	TAIR Copyright Conference Minutes

Related Links
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"jih ching chiu"

Return to Browse by Author
Sorting by Title	Sort by Date

Showing items 21-30 of 30 (3 Page(s) Totally)
<< < 1 2 3
View [10|25|50] records per page

Institution	Date	Title	Author
國立中山大學	2003	Data Item Placement for Load and Storage Balancing	Yung-Cheng Ma;Jih-Ching Chiu;Tien-Fu Chen;Chung-Ping Chung
國立中山大學	2002	Design of Instruction Address Queue for High Degree X86 Superscalar Architectures	Jih-Ching Chiu;Michael Jin-Yi Wang;Chung-Ping Chung
國立中山大學	2001	High-Bandwidth X86 Instruction Fetching Based on Instruction Pointer Table	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-12	The Fetch Mechanism Issue Of X86 Superscalar Processors with Fetch Rules	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-12	Improving ILP with Semantic Analyzer for Loop Unrolling in x86 Architectures	Jih-Ching Chiu;Zh-Lung Chen;Jean Jyh-Jiun Shann
國立中山大學	2000-09	Design of instruction stream buffer with trace support for X86 processors	Jih-Ching Chiu;I-Huan Huang;Chung-Ping Chung
國立中山大學	2000	The Design of the Decoding Unit with High Issue Rate for an X86 Superscalar Microprocessor	R-Ming Shiu;Jih-Ching Chiu;Shin-Ki Cheng;Jyh-Jiun Shann
國立中山大學	1999-05	Survey of Instruction Fetch/Decode Unit and Data Load/Store Unit of X86 Superscalar Microprocessors	R-Ming Shiu;Jih-Ching Chiu;Yuh-Horng Shiau;Jean Jyh-Jiun Shann;Chung-Ping Chung
國立中山大學	1999-04	Design and Implementation of Instruction Fetch/Decode Unit and Data Load/Store Unit of X86 Superscalar Microprocessors	R-Ming Shiu;Jih-Ching Chiu;Yuh-Horng Shiau;Jean Jyh-Jiun Shann;Chung-Ping Chung
國立中山大學	1997-10	Instruction Cache Prefetching with Extended BTB	Shi-An Chi;R-Ming Shiu;Jih-Ching Chiu;Si-En Chang;Chung-Ping Chung

Showing items 21-30 of 30 (3 Page(s) Totally)
<< < 1 2 3
View [10|25|50] records per page