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Showing items 1-25 of 111 (5 Page(s) Totally)
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| 臺大學術典藏 |
2022-09-21T23:31:01Z |
Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors
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Chen, Kai Hsun; Yang, Bo Yi; Liang, Jia Ruei; Chen, Hung Lin; JIUN-LANG HUANG |
| 臺大學術典藏 |
2021-07-15T05:32:57Z |
Opportunities for 2.5/3D Heterogeneous SoC Integration
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HUI-RU JIANG; YAO-WEN CHANG; JIUN-LANG HUANG; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:50:43Z |
A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays.
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Lin, Chen-Wei;Huang, Jiun-Lang; Lin, Chen-Wei; Huang, Jiun-Lang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:42Z |
Structural and optical properties of InGaN/GaN multiple quantum well light emitting diodes grown on (1122) facet GaN/sapphire templates by metalorganic chemical vapor deposition
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Huang, J.-L.;Wang, L.S.;Lai, Y.-S.;Lee, Y.-C.;Qiu, Z.R.;Liu, S.;Wuu, D.-S.;Feng, Z.C.; Huang, J.-L.; Wang, L.S.; Lai, Y.-S.; Lee, Y.-C.; Qiu, Z.R.; Liu, S.; Wuu, D.-S.; Feng, Z.C.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:42Z |
Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structures
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Feng, Z.C.; JIUN-LANG HUANG; Huang, J.-J.; Liu, L.;Wang, W.;Huang, J.-L.;Hu, X.;Chen, P.;Huang, J.-J.;Feng, Z.C.; Liu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P. |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Guest Editors' Introduction: A Promising Alternative to Conventional Silicon
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Huang, Jiun-Lang;Cheng, Kwang-Ting; Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
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Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:40Z |
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction
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Li, B.-Y.;Huang, J.-L.; Li, B.-Y.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:40Z |
An FPGA-Based Data Receiver for Digital IC Testing.
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Huang, Wei-Chen;Hou, Guan-Hao;Huang, Jiun-Lang;Kuo, Terry; Huang, Wei-Chen; Hou, Guan-Hao; Huang, Jiun-Lang; Kuo, Terry; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:39Z |
On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager
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Huang, X.-L.;Kang, P.-Y.;Huang, J.-L.;Chou, Y.-F.;Lee, Y.-P.;Kwai, D.-M.; Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:39Z |
FPAA implementation and validation of an SC integrator leakage measurement technique
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Du, N.-T.;Huang, J.-L.; Du, N.-T.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:39Z |
Image-quality-driven metrics for testing and calibrating ADC array in CMOS imagers: A first step
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Chang, H.-M.;Cheng, K.-T.;Huang, J.-L.; Chang, H.-M.; Cheng, K.-T.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:38Z |
A robust ADC code hit counting technique.
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Huang, Jiun-Lang;Chou, Kuo-Yu;Lu, Ming-Huan;Huang, Xuan-Lun; Huang, Jiun-Lang; Chou, Kuo-Yu; Lu, Ming-Huan; Huang, Xuan-Lun; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:38Z |
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime
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Chen, K.-H.;Chen, C.-Y.;Huang, J.-L.; Chen, K.-H.; Chen, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:37Z |
Improved weight assignment for logic switching activity during at-speed test pattern generation
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Wu, M.-F.;Pan, H.-C.;Wang, T.-H.;Huang, J.-L.;Tsai, K.-H.;Cheng, W.-T.; Wu, M.-F.; Pan, H.-C.; Wang, T.-H.; Huang, J.-L.; Tsai, K.-H.; Cheng, W.-T.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:37Z |
Foreword
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Wang, S.-J.;Huang, J.-L.; Wang, S.-J.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:36Z |
Diagnosing integrator leakage of single-bit first-order Δσ modulator using DC input
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Huang, X.-L.;Yang, C.-Y.;Huang, J.-L.; Huang, X.-L.; Yang, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:36Z |
Logic and Circuit Simulation
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Huang, J.-L.;Koh, C.-K.;Cauley, S.F.; Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:35Z |
Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs
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Huang, X.-L.;Kang, P.-Y.;Yu, Y.-C.;Huang, J.-L.; Huang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:35Z |
A robust ADC code hit counting technique
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Huang, J.-L.;Chou, K.-Y.;Lu, M.-H.;Huang, X.-L.; Huang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:26:16Z |
Design, automation, and test for low-power and reliable flexible electronics
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T.-C. Huang;J.-L. Huang;K.-T. Cheng; T.-C. Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:26:16Z |
A Test-Application-Count Based Learning Technique for Test Time Reduction
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G.-Y. Lin;K.-H. Tsai;J.-L. Huang;W.-T. Cheng; G.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:00:40Z |
FPGA-Based Subset Sum Delay Lines
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C.-Y. Wang;Y.-Y. Chen;J.-L. Huang;X.-L. Huang; C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:00:40Z |
數位類比轉換器的元素的權重的估算方法、裝置及應用其之逐次逼近暫存 器類比數位轉換器
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陳弘易;陳昶聿;黃炫倫;黃俊郎; 陳弘易; 陳昶聿; 黃炫倫; 黃俊郎; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN
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Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
Showing items 1-25 of 111 (5 Page(s) Totally)
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