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"jou jing yang"的相關文件
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| 國立交通大學 |
2014-12-08T15:11:01Z |
Verification of pin-accurate port connections
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Lee, Geeng-Wei; Huang, Juinn-Dar; Wang, Chun-Yao; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:10:04Z |
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
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Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:23Z |
A precise bandwidth control arbitration algorithm for hard real-time SoC buses
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Lin, Bu-Ching; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:09Z |
Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
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Wu, Meng-Chen; Lu, Ming-Ching; Chen, Hung-Ming; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:04:49Z |
A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus
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Cheng, Kuang-Chin; Jou, Jing-Yang |
| 國立臺灣大學 |
2006-10 |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
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Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 臺大學術典藏 |
2006-10 |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
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Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang; Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2006 |
Reliable crosstalk-driven interconnect optimization
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Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
| 臺大學術典藏 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan; Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
| 國立臺灣大學 |
2003 |
Inductance Modeling for On-Chip Interconnects
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Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen; Chen, Tai-Chen; Jou, Jing-Yang |
| 臺大學術典藏 |
2003 |
Inductance Modeling for On-Chip Interconnects
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Chen, Tai-Chen; Jou, Jing-Yang; Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen; Chen, Tai-Chen; Jou, Jing-Yang; Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen |
| 國立臺灣大學 |
2000 |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
1996-11 |
An efficient PRPG strategy by utilizing essential faults
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Huang, Li-Ren; Jou, Jing-Yang; Kuo, Sy-Yen |
| 國立臺灣大學 |
1996-11 |
Easily testable data path allocation using input/output registers
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Huang, Li-Ren; Jou, Jing-Yang; Kuo, Sy-Yen; Liao, Wen-Bin |
顯示項目 96-110 / 110 (共5頁)
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