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Taiwan Academic Institutional Repository >
Browse by Author
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"jou jy"
Showing items 6-15 of 67 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:47:21Z |
On circuit clustering for area/delay tradeoff under capacity and pin constraints
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Huang, JD; Jou, JY; Shen, WZ; Chuang, HH |
| 國立交通大學 |
2014-12-08T15:46:14Z |
A structure-oriented power modeling technique for macrocells
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Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:46:03Z |
Internet-based hierarchical floorplan design
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Lin, JH; Jou, JY; Jiang, IHR |
| 國立交通大學 |
2014-12-08T15:45:37Z |
On computing the minimum feedback vertex set of a directed graph by contraction operations
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Lin, HM; Jou, JY |
| 國立交通大學 |
2014-12-08T15:45:10Z |
An automatic controller extractor for HDL descriptions at the RTL
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Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:59Z |
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
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Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:44:51Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
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Jiang, IHR; Chang, YW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:35Z |
Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs
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Chuang, HH; Jou, JY; Shung, CB |
| 國立交通大學 |
2014-12-08T15:44:32Z |
A new method for constructing IP level power model based on power sensitivity
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Huang, HL; Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:23Z |
Efficient coverage analysis metric for HDL design validation
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Liu, CN; Jou, JY |
Showing items 6-15 of 67 (7 Page(s) Totally)
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