臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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机构	日期	题名	作者
臺大學術典藏	2018-09-10T15:00:41Z	Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits	C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; YI-CHANG LU; CHIEN-MO LI
臺大學術典藏	2018-09-10T15:00:41Z	Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits	C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; YI-CHANG LU; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:50:54Z	Testing Leakage Faults of Power TSV in 3D IC	Chi-Jih Shih;Shih-An Hsieh;Yi-Chang Lu;James Chien-Mo Li;Tzong-Lin Wu;K. Chakrabarty; Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:50:54Z	Testing Leakage Faults of Power TSV in 3D IC	Chi-Jih Shih;Shih-An Hsieh;Yi-Chang Lu;James Chien-Mo Li;Tzong-Lin Wu;K. Chakrabarty; Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:50:54Z	Test Generation of Path Delay Faults Induced by Defects in Power TSV	Chi-Jih Shih;Shih-An Hsieh;Yi-Chang Lu;James Chien-Mo Li;Tzong-Lin Wu;K. Chakrabarty; Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:50:54Z	Test Generation of Path Delay Faults Induced by Defects in Power TSV	Chi-Jih Shih;Shih-An Hsieh;Yi-Chang Lu;James Chien-Mo Li;Tzong-Lin Wu;K. Chakrabarty; Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC	C. J. Shih;C. Y. Hsu;C. Y. Kou;J. C. M. Li;J. C. Rau;K. Chakrabarty; C. J. Shih; C. Y. Hsu; C. Y. Kou; J. C. M. Li; J. C. Rau; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC	C. J. Shih;C. Y. Hsu;C. Y. Kou;J. C. M. Li;J. C. Rau;K. Chakrabarty; C. J. Shih; C. Y. Hsu; C. Y. Kou; J. C. M. Li; J. C. Rau; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,	C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,	C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI

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