English  |  正體中文  |  简体中文  |  Total items :2823024  
Visitors :  30260337    Online Users :  803
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
About TAIR

Browse By

News

Copyright

Related Links

"ker md"

Return to Browse by Author
Sorting by Title Sort by Date

Showing items 51-75 of 129  (6 Page(s) Totally)
<< < 1 2 3 4 5 6 > >>
View [10|25|50] records per page

Institution Date Title Author
國立交通大學 2014-12-08T15:27:05Z New diode string design with very low leakage current for using in power supply ESD clamp circuits Ker, MD; Lo, WY; Chang, HH
國立交通大學 2014-12-08T15:26:55Z Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology Ker, MD; Hong, KK; Chen, TY; Tang, H; Huang, SC; Chen, SS; Huang, CT; Wang, MC; Loh, YT
國立交通大學 2014-12-08T15:26:55Z ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design Chen, TY; Ker, MD
國立交通大學 2014-12-08T15:26:55Z Level shifters for high-speed 1-v to 3.3-v interfaces in a 0.13-mu m Cu-Interconnection/Low-k CMOS technology Wang, WT; Ker, MD; Chiang, MC; Chen, CH
國立交通大學 2014-12-08T15:26:51Z Design on ESD protection circuit with very low and constant input capacitance Chen, TY; Ker, MD
國立交通大學 2014-12-08T15:26:51Z Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process Ker, MD; Lo, WY; Chen, TY; Tang, H; Chen, SS; Wang, MC
國立交通大學 2014-12-08T15:26:50Z Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's Ker, MD; Jiang, HC; Peng, JJ; Shieh, TL
國立交通大學 2014-12-08T15:26:50Z ESD test methods on integrated circuits: An overview Ker, MD; Peng, JH; Jiang, HC
國立交通大學 2014-12-08T15:26:45Z Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology Ker, MD; Jiang, HC
國立交通大學 2014-12-08T15:26:45Z ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration Ker, MD; Chuang, CH
國立交通大學 2014-12-08T15:26:45Z Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS process Ker, MD; Hung, KK; Tang, HTH; Huang, SC; Chen, SS; Wang, MC
國立交通大學 2014-12-08T15:26:43Z Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process Ker, MD; Chuang, CH; Lo, WY
國立交通大學 2014-12-08T15:26:38Z ESD protection circuits with novel MOS-bounded diode structures Ker, MD; Chuang, CH
國立交通大學 2014-12-08T15:26:38Z Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits Peng, JJ; Ker, MD; Jiang, HC
國立交通大學 2014-12-08T15:26:37Z On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:26:36Z ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins Ker, MD; Chang, CY; Chang, YS
國立交通大學 2014-12-08T15:26:36Z Design of negative charge pump circuit with polysilicon diodes in a 0.25-mu m CMOS process Ker, MD; Chang, CY; Jiang, HC
國立交通大學 2014-12-08T15:26:35Z Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness Ker, MD; Hsu, HC; Peng, JH
國立交通大學 2014-12-08T15:26:34Z ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process Ker, MD; Chuang, CH; Hsu, KC; Lo, WY
國立交通大學 2014-12-08T15:26:31Z ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness Ker, MD; Lo, WY; Lee, CM; Chen, CP; Kao, HS
國立交通大學 2014-12-08T15:26:31Z ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness Ker, MD; Lo, WY; Lee, CM; Chen, CP; Kao, HS
國立交通大學 2014-12-08T15:26:29Z Complementary substrate-triggered SCR devices for on-chip ESD protection circuits Ker, MD; Hsu, KC
國立交通大學 2014-12-08T15:26:28Z Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution Ker, MD; Peng, JJ; Jiang, HC
國立交通大學 2014-12-08T15:26:23Z Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuits Ker, MD; Hsu, HC; Peng, JJ
國立交通大學 2014-12-08T15:26:22Z Novel electrostatic discharge protection design for nanoelectronics in nanoscale CMOS technology Ker, MD; Tseng, TK

Showing items 51-75 of 129  (6 Page(s) Totally)
<< < 1 2 3 4 5 6 > >>
View [10|25|50] records per page