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Taiwan Academic Institutional Repository >
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"ker md"
Showing items 76-100 of 129 (6 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:26:21Z |
MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS process
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Ker, MD; Lin, KH; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:26:21Z |
Evaluation on ESD robustness of UPS diode and TFT device by transmission line pulsing (TLP) technique
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Ker, MD; Tseng, TK; Yang, SC; Shih, A; Tsai, YM |
| 國立交通大學 |
2014-12-08T15:26:15Z |
Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit
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Ker, MD; Tsai, CS |
| 國立交通大學 |
2014-12-08T15:26:14Z |
ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique
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Ker, MD; Hsu, HC |
| 國立交通大學 |
2014-12-08T15:26:13Z |
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's
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Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:09Z |
A novel LC-Tank ESD protection design for giga-Hz RF circuits
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Ker, MD; Chou, CI; Lee, CM |
| 國立交通大學 |
2014-12-08T15:26:04Z |
Interference of esd protection diodes on RF performance in GIGA-HZ RF circuits
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Ker, MD; Lee, CM |
| 國立交通大學 |
2014-12-08T15:25:56Z |
Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuits
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Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:25:51Z |
Correlation between transmission-line-pulsing I-V curve and human-body-model ESD level on low temperature poly-Si TFT devices
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Ker, MD; Hou, CL; Chang, CY; Chu, FT |
| 國立交通大學 |
2014-12-08T15:25:51Z |
Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces
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Chang, WJ; Ker, MD |
| 國立交通大學 |
2014-12-08T15:25:51Z |
Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels
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Ker, MD; Chang, WJ; Lo, WY |
| 國立交通大學 |
2014-12-08T15:25:51Z |
Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes
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Ker, MD; Chen, WY |
| 國立交通大學 |
2014-12-08T15:25:49Z |
Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process
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Ker, MD; Wu, WL; Chang, CY |
| 國立交通大學 |
2014-12-08T15:25:49Z |
Test structures to verify ESD robustness of on-glass devices in UPS technology
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Ker, MD; Deng, CK; Yang, SC; Tasi, YM |
| 國立交通大學 |
2014-12-08T15:25:47Z |
ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme
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Ker, MD; Kuo, BJ |
| 國立交通大學 |
2014-12-08T15:25:44Z |
A new output buffer for 3.3-V PCI-X application in a 0.13-mu m 1/2.5-V
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Chen, SL; Ker, MD |
| 國立交通大學 |
2014-12-08T15:25:43Z |
Transient-induced latchup in CMOS technology: Physical mechanism and device simulation
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Ker, MD; Hsu, SF |
| 國立交通大學 |
2014-12-08T15:25:38Z |
Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
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Ker, MD; Chen, JH; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:25:38Z |
Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology
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Hsu, HC; Chen, CM; Ker, MD |
| 國立交通大學 |
2014-12-08T15:25:32Z |
ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications
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Ker, MD; Chang, WJ; Yang, M; Chen, CC; Chan, MC; Shieh, WT; Yen, KL |
| 國立交通大學 |
2014-12-08T15:25:24Z |
New curvature-compensation technique for CMOS bandgap reference with sub-1-v operation
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Ker, MD; Chen, JS; Chu, CY |
| 國立交通大學 |
2014-12-08T15:25:23Z |
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications
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Ker, MD; Chen, SL; Tsai, CS |
| 國立交通大學 |
2014-12-08T15:25:22Z |
Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger
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Ker, MD; Hsu, SF |
| 國立交通大學 |
2014-12-08T15:25:22Z |
Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process
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Chen, JS; Ker, MD |
| 國立交通大學 |
2014-12-08T15:25:22Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
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Ker, MD; Chen, WY; Hsu, KC |
Showing items 76-100 of 129 (6 Page(s) Totally)
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