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Showing items 11-35 of 40 (2 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-29T01:20:14Z |
Test Pattern Modification for Average IR-Drop Reduction
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Ding, W.-S.;Hsieh, H.-Y.;Han, C.-Y.;Li, J.C.-M.;Wen, X.; Ding, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:13Z |
A multicircuit simulator based on inverse jacobian matrix reuse
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Lee, H.-I.;Han, C.-Y.;Li, J.C.-M.; Lee, H.-I.; Han, C.-Y.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:12Z |
Placement optimization of flexible TFT digital circuits
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Liu, W.-H.;Ma, E.-H.;Wei, W.-E.;Li, J.C.-M.; Liu, W.-H.; Ma, E.-H.; Wei, W.-E.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:12Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
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Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:10Z |
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
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Chiang, K.-Y.;Ho, Y.-H.;Chen, Y.-W.;Pan, C.-S.;Li, J.C.-M.; Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:09Z |
Fault Simulation and Test Generation
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Li, J.C.-M.;Hsiao, M.S.; Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-16T06:36:17Z |
Test generation of path delay faults induced by defects in power TSV
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Shih, C.-J.;Hsieh, S.-A.;Lu, Y.-C.;Li, J.C.-M.;Wu, T.-L.;Chakrabarty, K.; Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; Chakrabarty, K.; YI-CHANG LU |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
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Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:45:49Z |
An at-speed self-testable technique for the high speed domino adder
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Wang, Y.-S.;Hsieh, M.-H.;Liu, C.-M.;Liu, C.-W.;Li, J.C.-M.;Chen, C.C.-P.; Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Liu, C.-W.; Li, J.C.-M.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:15:26Z |
Test generation of path delay faults induced by defects in power TSV
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Shih, C.-J.;Hsieh, S.-A.;Lu, Y.-C.;Li, J.C.-M.;Wu, T.-L.;Chakrabarty, K.; Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; Chakrabarty, K.; TZONG-LIN WU |
| 臺大學術典藏 |
2019-04-22T05:22:34Z |
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction
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Jiang, J.-H.R.;Li, J.C.M.;Pai, Y.-C.;Wen, H.-T.;Wang, J.-J.;Pai, C.-C.;Wang, R.-Y.;Chang, Y.-W.; Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W.; Li, J.C.M.; Jiang, J.-H.R. |
| 臺大學術典藏 |
2018-09-10T08:34:44Z |
An accurate timing-aware diagnosis algorithm for multiple small delay defects
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Chen, P.-J.;Hsu, W.-L.;Li, J.C.-M.;Tseng, N.-H.;Chen, K.-Y.;Changchien, W.-P.;Liu, C.C.C.; Chen, P.-J.; Hsu, W.-L.; Li, J.C.-M.; Tseng, N.-H.; Chen, K.-Y.; Changchien, W.-P.; Liu, C.C.C.; WEI-LI HSU; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
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Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
Static timing analysis for flexible TFT circuits
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Chao-Hsuan Hsu;Liu, C.;En-Hua Ma;Li, J.C.-M.; Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:14:25Z |
Reliability screening of a-Si TFT circuits: Very-low voltage and I DDQ Testing
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Shen, S.-T.;Liu, C.;Ma, E.-H.;Cheng, I.-C.;Li, J.C.-M.; Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:36:19Z |
Very-low-voltage testing of amorphous silicon TFT circuits
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Shen, S.-T.;Liu, W.-H.;Ma, E.-H.;Li, J.C.-M.;Cheng, I.-C.; Shen, S.-T.; Liu, W.-H.; Ma, E.-H.; Li, J.C.-M.; Cheng, I.-C.; I-CHUN CHENG |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains
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Li, J. C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC
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Li, J. C.-M.; E. J. McCluskey; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains
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Li, J. C. M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T04:59:51Z |
A Design for Testability Technique for Low Power Delay Fault Testing
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Li, J. C. M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T04:15:41Z |
Diagnosis for Sequence Dependent Chips
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Li, J. C.M.; E. J. McCluskey; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T03:50:57Z |
Testing for Resistive and Stuck Opens
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Li, J. C.M.; Tseng, C.W.; E.J. McCluskey; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T03:50:57Z |
Diagnosis of Tunneling Opens
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Li, J. C.M.; E.J. McCluskey; CHIEN-MO LI |
| 國立臺灣大學 |
2010 |
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in
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Kao, Wei-Chung; Chuang, Wei-Shun; Lin, Hsiu-Ting; Li, J.C.-M.; Manquinho, V. |
| 國立臺灣大學 |
2009 |
Time-space test response compaction and diagnosis based on BCH codes
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Wang, F.-M.; Wang, W.-C.; Li, J.C.-M. |
Showing items 11-35 of 40 (2 Page(s) Totally)
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