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"liu shen iuan"
Showing items 111-120 of 185 (19 Page(s) Totally)
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| 國立臺灣大學 |
2003 |
CMOS magnetic field to frequency converter
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Chen, Shr-Lung; Kuo, Chien-Hung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
Analysis of on-chip spiral inductors using the distributed capacitance model
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Wu, Chia-Hsin; Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
An 800Mb/s tracking clock recovery receiver for the IEEE P1394a serial bus
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Chang, Hsiang-Hui; Dehng, Giang-Kaai; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
CMOS Tunable 1/x Circuit and its Applications
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Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
A sub-1V fourth-order bandpass delta-sigma modulator
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Chang, Hsiang-Hui; Kuo, Chien-Hung; Liu, Ming-Huang; Liu, Shen-Iuan |
| 淡江大學 |
2002-12 |
Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm
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Kuo, Chien-hung; Hsueh, Tzu-chien; Liu, Shen-iuan |
| 國立臺灣大學 |
2002-08 |
Analysis of on-chip spiral inductors using the distributed capacitance model
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Wu, Chia-Hsin; Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
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Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 臺大學術典藏 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
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Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
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Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
Showing items 111-120 of 185 (19 Page(s) Totally)
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