| 國立臺灣大學 |
2003 |
CMOS magnetic field to frequency converter
|
Chen, Shr-Lung; Kuo, Chien-Hung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
Analysis of on-chip spiral inductors using the distributed capacitance model
|
Wu, Chia-Hsin; Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
An 800Mb/s tracking clock recovery receiver for the IEEE P1394a serial bus
|
Chang, Hsiang-Hui; Dehng, Giang-Kaai; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
CMOS Tunable 1/x Circuit and its Applications
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2003 |
A sub-1V fourth-order bandpass delta-sigma modulator
|
Chang, Hsiang-Hui; Kuo, Chien-Hung; Liu, Ming-Huang; Liu, Shen-Iuan |
| 淡江大學 |
2002-12 |
Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm
|
Kuo, Chien-hung; Hsueh, Tzu-chien; Liu, Shen-iuan |
| 國立臺灣大學 |
2002-08 |
Analysis of on-chip spiral inductors using the distributed capacitance model
|
Wu, Chia-Hsin; Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 臺大學術典藏 |
2002-08 |
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
|
Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
|
Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
A wide-range and fixed latency of one clock cycle delay-locked loop
|
Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network
|
Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-05 |
Analysis and application of miniature 3D inductor
|
Wu, Chia-Hsin; Tang, Chih-Chun; Chiu, Chi-Kun; Liu, Shen-Iuan |
| 臺大學術典藏 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
|
Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei |
| 臺大學術典藏 |
2002-05 |
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network
|
Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan; Tang, Chih-Chun; Wu, Chia-Hsin; Li, Kun-Hsien; Lee, Tai-Cheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002-04 |
2.4 GHz offset-cancelling down-conversion mixer
|
Tang, Chih-Chun; Li, Kun-Hsien; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002 |
Miniature 3-D Inductors in Standard CMOS Process
|
Tang, Chih-Chun; Wu, Chia-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002 |
A wide-range delay-locked loop with a fixed latency of one clock cycle
|
Chang, Hsiang-Hui; Lin, Jyh-Woei; Yang, Ching-Yuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002 |
Systematic generation of current-mode linear transformation filters based on multiple output CCIIs
|
Hwang, Yuh-Shyan; Hung, Pei-Tzu; Chen, Wei; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002 |
A 1V 5.8GHz low noise amplifier in a 0.35um standard CMOS process
|
Tang, Chih-Chun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2002 |
Multi-bit delta-sigma modulator using a modified DWA algorithm
|
Kuo, Chien-Hung; Hsueh, Tzu-Chien; Liu, Shen-Iuan |
| 淡江大學 |
2001-10 |
CMOS oversampling Delta-Sigma magnetic-to-digital converters
|
Kuo, Chien-hung; Chen, Shr-lung; Ho, Lee-an; Liu, Shen-iuan |
| 淡江大學 |
2001-05 |
CMOS oversampling ΔΣ magnetic to digital converters
|
Ho, Lee-an; Chen, Shr-lung; Kuo, Chien-hung; Liu, Shen-iuan |
| 國立臺灣大學 |
2001-05 |
CMOS oversampling /spl delta//spl Sigma/ magnetic to digital converters
|
Ho, Lee-An; Chen, Shr-Lung; Kuo, Chien-Hung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2001-05 |
A fast-lock mixed-mode DLL using a 2-b SAR algorithm
|
Dehng, Guang-Kaai; Lin, Jyh-Woei; Liu, Shen-Iuan |
