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Taiwan Academic Institutional Repository >
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"liu shen iuan"
Showing items 31-40 of 185 (19 Page(s) Totally)
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| 國立臺灣大學 |
2008-10 |
A 3~8GHz delay-locked loop with cycle jitter calibration
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Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-07 |
A 81.5~85.9GHz injection-locked frequency divider in 65nm CMOS
|
Cho, Lan-Chou; Tsai, Kun-Hung; Hung, Chao-Ching; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-03 |
40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-02 |
An all-digital fast-locking programmable DLL-based clock generator
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Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A digital calibration technique for charge pumps in phase-locked systems
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Liang, Che-Fu; Chen, Shin-Hua; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator
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Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier
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Wang, I-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS
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Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
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Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-μm CMOS
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Lee, Chihun; Cho, Lan-Chou; Wu, Jia-Hao; Liu, Shen-Iuan |
Showing items 31-40 of 185 (19 Page(s) Totally)
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