| 國立臺灣大學 |
2008-10 |
A 3~8GHz delay-locked loop with cycle jitter calibration
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-07 |
A 81.5~85.9GHz injection-locked frequency divider in 65nm CMOS
|
Cho, Lan-Chou; Tsai, Kun-Hung; Hung, Chao-Ching; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-03 |
40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008-02 |
An all-digital fast-locking programmable DLL-based clock generator
|
Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A digital calibration technique for charge pumps in phase-locked systems
|
Liang, Che-Fu; Chen, Shin-Hua; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator
|
Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier
|
Wang, I-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
|
Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-μm CMOS
|
Lee, Chihun; Cho, Lan-Chou; Wu, Jia-Hao; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration
|
Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
10-Gb/s Inductorless CDRs With Digital Frequency Calibration
|
Liang, Che-Fu; Chu, Hong-Lin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A delay-locked loop with statistical background calibration
|
Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
|
Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line
|
Chen, Chao-Chyun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs
|
Lin, Shao-Hung; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:34:31Z |
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution
|
Chen, Poki;Liu, Shen-Iuan; Chen, Poki; Liu, Shen-Iuan |
| 臺大學術典藏 |
2007-04-19T04:12:30Z |
CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure
|
Wu, Yan-Pei; Chen, Jiann-Jong; Liu, Shen-Iuan; Tsay, Jiann-Horng; Tsay, Jiann-Horng; Liu, Shen-Iuan; Chen, Jiann-Jong; Wu, Yan-Pei |
| 國立臺灣大學 |
2007 |
A time-constant calibrated phase-locked loop with a fast-locked time
|
Han, Sung-Rung; Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A CMOS 5-bit 5GSample/sec analog-to-digital converter in 0.13um CMOS
|
Wang, I-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS
|
Chen, Ke-Hou; Lu, Jian-Hao; Chen, Bo-Jiun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A multi-band burst-mode clock and data recovery circuit
|
Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A capacitor multiplication technique using a second-generation current conveyor in the loop filter of the phase-locked loops
|
Chen, Chao-Chyun; Lee, Sheng-Chou; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology
|
Cho, Lan-Chou; Lee, Chihun; Liu, Shen-Iuan |
