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Taiwan Academic Institutional Repository >
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"liu shen iuan"
Showing items 36-45 of 185 (19 Page(s) Totally)
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| 國立臺灣大學 |
2008 |
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator
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Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier
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Wang, I-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS
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Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
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Liang, Che-Fu; Hwu, Sy-Chyuan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-μm CMOS
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Lee, Chihun; Cho, Lan-Chou; Wu, Jia-Hao; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration
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Chuang, Chi-Nan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
10-Gb/s Inductorless CDRs With Digital Frequency Calibration
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Liang, Che-Fu; Chu, Hong-Lin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A delay-locked loop with statistical background calibration
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Kao, Shao-Ku; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
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Liao, Chih-Fan; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line
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Chen, Chao-Chyun; Liu, Shen-Iuan |
Showing items 36-45 of 185 (19 Page(s) Totally)
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